Description
Lab Objectives
This lab is a refresher to the finite state machines that you learned in EE 271 by designing a parking lot
occupancy counter.
Laboratory Design Kits
We will use the DE1-SoC development board that you used in EE 271. Please pick up your lab kit from
the EE store.
Using Quartus II Software
The Quartus II web edition release 17.0 is preloaded on the machines in the department, and you can do all the
work on these PCs. However, if you have a PC of your own that you would like to use, you can install the
software for free. To install the software, go to
http://fpgasoftware.intel.com/17.0/?edition=lite&platform=windows&download_manager=dlm3 , choose
version 17.0 from the top drop-down menu, download the free web edition and install it. Note that you will
have to register to be able to download the software.
The file to download is the 5.8 GB tar file under the
“Combined files” tab. Extract the tar file using a program like 7-zip and run the QuartusLiteSetup-17.0-
windows.exe file. When it asks for the components to install, make sure you select each of these:
Quartus Prime Lite Edition
(Free) Devices: Cyclone V
ModelSim: Intel FPGA Starter Edition (Free)
When the software is done, make sure to install the USBblaster driver. Run Quartus next, and if
asked about licensing just run the software (we use the free version, so no license required).
NOTE: If you have trouble accessing the website to download the software, you can download it from
this google drive. (you need to login using your netID)
https://drive.google.com/open?id=1Tl_1G_DFn6Yps0DuEh3yUAr4vXpJ48SF
Task 0: Warm up exercise on Quartus and ModelSim
This task is a refresher on creating a Quartus project, writing a SystemVerilog program and simulating
it in ModelSim. You can skip this task if you do not need a refresher.
For this task, follow along a series of video tutorials that will walk you through the steps of creating a full
adder using SystemVerilog and simulating the design in ModelSim. For your reference, the source code
used in the tutorials is in the appendix of this document.
Please follow the tutorials in the following order:
1. Launch the Quartus Prime software.
2. Create a project from scratch. Please follow the steps in the following videos and use the same
project name as in the video
3. Implement the full adder using SystemVerilog and simulate it using ModelSim. Please follow the
following video: Please note that in the video when it refers to compiling the project for the first
time, it may give you a compilation error. If you run the video for few more seconds it’ll tell you
about setting the top level modules so that the program compiles.
3. Mapping a SystemVerilog design to an FPGA.
5. Loading the design onto the FPGA. Please follow the steps in the following video and test
your full adder on the DE1_SoC board and verify that it matches the truth table.
After completing this task, you should create future projects in a similar fashion and use SystemVerilog
and ModelSim accordingly.
Assigned Task
Parking Lot Occupancy Counter
Consider a parking lot with a single entry and exit gate. Two pairs of photo sensors are used to monitor
the activity of cars, as shown in Figure 1. When an object is between the photo transmitter and the photo
receiver, the light is blocked, and the corresponding output is asserted to 1. By monitoring the events of
two sensors, we can determine whether a car is entering or exiting, or a pedestrian is passing through. For
example, the following sequence indicates that a car enters the lot:
• Initially, both sensors are unblocked (i.e., the a and b signals are “00”).
• Sensor a is blocked (i.e., the a and b signals are “10″).
• Both sensors are blocked (i.e., the a and b signals are “11”).
• Sensor a is unblocked (i.e., the a and b signals are “01”).
• Both sensors become unblocked (i.e., the a and b signals are “00”).
Figure 1 Parking lot sensors
Design a parking lot occupancy counter as follows:
1. Design an FSM with two input signals, a and b, and two output signals, enter and
exit. The enter and exit signals assert true for one clock cycle when a car enters or exits the lot,
respectively. Derive the SystemVerilog code for the FSM and simulate it in ModelSim. You may
assume that cars will not change direction while entering or exiting the parking lot.
2. Design a counter with two control signals, inc and dec, which increment and decrement the
counter when asserted. Assume that the maximum capacity of the parking lot is 25 spots. Derive
the SystemVerilog code for the FSM and simulate it in ModelSim.
3. Combine the counter and the FSM and model the parking lot, using push buttons to mimic the
two sensor outputs and the seven-segment displays to display the car count.
EE 371 Lab 1 Parking Lot Occupancy Counter
Your system should have the following:
a. Display the car counts as they enter the parking lot on the seven-segment
displays HEX0 and HEX1.
b. If the counter reaches 25, display the word “FULL” on HEX5-HEX2
c. As cars exit the lot, the counter decrements and the corresponding number should
be displayed on HEX0 and HEX1.
d. When the lot is empty. Display the word “CLEAR” on HEX5-HEX1 and display the
number ‘0’ on HEX0.
e. Use 2 off-board LEDs to represent the a and b signals. When a is 1, turn on a red
LED, and when a is 0, turn off a red LED. Stimulatingly, when b is 1, turn on a green
LED, and when b is 0, turn off a green LED.
4. Connecting off board components requires the use of GPIO of the DE1-SoC board. Please
refer to “GPIO guide” document for information on how to use the GPIO port.
5. Simulate the system in ModelSim.
6. Download the program to the DE1_SoC board and demonstrate it to your TA.
7. Create a block diagram for your system and include it in your lab report.
8. In the report, include the state diagram(s) that you used in designing this system
Lab Demonstration and Submission Requirements
• Submit a short lab report (as short as 3 pages or as many as you need) that should include 3
main sections, detailed as follows:
Procedure
– Include block diagram of the system and FSM diagrams
– Discuss each major component of the system:
– Highlight important features, and
– Discuss how and why you implemented it the way you did
– Include limited screenshots of important pieces of code if helpful to the discussion
EE 371 Lab 1 Parking Lot Occupancy Counter
Results
– Include screenshots of ModelSim results for important modules
– Describe what you tested in the simulation, and what the results in the screenshot show
– Give a brief overview of the finished project, compared to what was asked
Problems Faced & Feedback
– Describe any issues you had while completing the lab, and how/if you were able to
overcome them.
– Include tips and tricks that you found out about to complete the lab. These tips could be
very useful for you in the future.
– Include how many hours spent on finishing the lab, including reading, planning, design,
coding, debugging, testing, etc. Everything related to the lab (in total).
– Give any other positive or negative feedback you have on the lab.
• Submit the SystemVerilog files of your parking lot occupancy counter and the ModelSim
waveforms of all modules. Part of your grade will be based on how well you comment your
code. Please refer to the “Commenting code” document for guidelines.
• Submit the Flow Summary (produced during compilation) of compiling your system.
• Submit your report and programs to Canvas.
Appendix
Source code used in the videos
1. FullAdder module
2. DE1_Soc module
EE 371 Lab 1 Parking Lot Occupancy Counter
