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# ECEN 651 Laboratory Exercise 2 solution

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## Behavioral, Dataflow, and Structural Verilog Objective

The objective of lab this week is to explain the various levels of abstraction used to model digital logic
in Verilog, while reviewing a few architectural level digital components. In Verilog, digital logic can be
described in three distinct ways. At one end of the spectrum is structural modeling such that digital logic is
conveyed using primitive logic gates.

At the other end of the spectrum is behavioral in which a particular
circuit behavior is simply described. Somewhere between these two is a method which allows the designer to
express how data should flow through the digital circuitry using logic and arithmetic expressions. Typically,
a design will consist of a mixture of the aforementioned design description levels. Experience developing
hardware in Verilog will reveal which level is more appropriate for a given circumstance.

## Procedure

1. Design and simulate a JK Flip-flop using structural Verilog.
(a) Using Figure 1 as a reference, describe a JK Flip-flop in structural Verilog.
1
2 Laboratory Exercise #2
NAND
NAND
NAND
NAND
Q
~Q
J
Clk
K
~R

Figure 1: A JK Flip-Flop constructed with NAND gates
(b) Use the code provide below to test your structural model of the JK flip-flop. Demonstrate your
progress to the TA.
Note the use of blocking assignment statements in the code below.
‘ d e f i n e STRLEN 15
module J K T e st v ;
t a s k p a s s T e s t ;

i n p u t a ct u al O ut , e x p e ct e d O ut ;
i n p u t [ ‘STRLEN∗ 8 : 0 ] t e s t T y p e ;
i n o u t [ 7 : 0 ] p a s s e d ;
i f ( a c t u a l O u t == e x p e ct e d O ut )
b e gi n
\$ d i s p l a y (”% s p a s s e d ” , t e s t T y p e ) ;
p a s s e d = p a s s e d + 1 ;
end
e l s e

\$ d i s p l a y (”% s f a i l e d : %d s h o ul d be %d ” ,
t e st T y p e , a ct u al O ut , e x p e ct e d O ut ) ;
e n d t a s k
t a s k a l l P a s s e d ;
2 ECEN 651
Laboratory Exercise #2 3
i n p u t [ 7 : 0 ] p a s s e d ;

i n p u t [ 7 : 0 ] n umTe st s ;
i f ( p a s s e d == n umTe st s )
\$ d i s p l a y ( ” All t e s t s p a s s e d ” ) ;
e l s e
\$ d i s p l a y ( ” Some t e s t s f a i l e d ” ) ;
e n d t a s k
/ / I n p u t s
r e g j ;
r e g k ;
r e g c l k ;
r e g r e s e t ;

r e g [ 7 : 0 ] p a s s e d ;
/ / O ut p ut s
wi r e o ut ;
/ / I n s t a n t i a t e t h e U nit Under T e st (UUT)
JK u ut (
. o ut ( o ut ) ,
. j ( j ) ,
. k ( k ) ,
. c l k ( c l k ) ,
. r e s e t ( r e s e t )
) ;

i n i t i a l b e gi n
/ / I n i t i a l i z e I n p u t s
j = 0 ;
k = 0 ;
c l k = 0 ;
r e s e t = 1 ;
p a s s e d = 0 ;
/ / Wait 100 n s f o r g l o b a l r e s e t t o f i n i s h
# 1 0 0;
ECEN 651 3
4 Laboratory Exercise #2

/ / Add s t i m u l u s h e r e
r e s e t = 0 ;
# 9 0; j = 1; k = 0; # 7; c l k = 1 ;
# 3; c l k = 0 ; # 9 0;
p a s s T e s t ( o ut , 1 , ” S et ” , p a s s e d ) ;
# 9 0; j = 1; k = 1; # 7; c l k = 1 ;
# 3; c l k = 0 ; # 9 0;

p a s s T e s t ( o ut , 0 , ” T o g gle 1 ” , p a s s e d ) ;
# 9 0; j = 0; k = 0; # 7; c l k = 1 ;
# 3; c l k = 0 ; # 9 0;
p a s s T e s t ( o ut , 0 , ” Hold 1 ” , p a s s e d ) ;
# 9 0; j = 1; k = 1; # 7; c l k = 1 ;
# 3; c l k = 0 ; # 9 0;

p a s s T e s t ( o ut , 1 , ” T o g gle 2 ” , p a s s e d ) ;
# 9 0; j = 0; k = 0; # 7; c l k = 1 ;
# 3; c l k = 0 ; # 9 0;
p a s s T e s t ( o ut , 1 , ” Hold 2 ” , p a s s e d ) ;
# 9 0; j = 0; k = 1; # 7; c l k = 1 ;
# 3; c l k = 0 ; # 9 0;

p a s s T e s t ( o ut , 0 , ” R e s et ” , p a s s e d ) ;
# 9 0; a l l P a s s e d ( p a s s e d , 6 ) ;
end
endmodule
(c) Provide a truth table to describe the operation of a JK Flip-flop.
2. Design and simulate a JK and D Flip-flop using behavioral Verilog.
(a) In behavioral Verilog, create a JK Flip-flop module. Be sure to use non-blocking assignment
statements.
4 ECEN 651
Laboratory Exercise #2 5

(b) Test your module against the test bench provided above. The operation should be identical to
(c) Now create a D Flip-flop using behavioral Verilog and provide the truth table for a D flip-flop.
(d) Using the above testbench as a starting point, create a testbench to test the operation of your D
Flip-flop. Demonstrate your progress to the TA.
3. Design and simulate a 2-to-4 decoder using dataflow Verilog.
(a) Construct the truth table for a 2:4 decoder with an enable signal.

(b) Draw the gate level schematic for a 2:4 decoder.
(c) Describe the decoder in Verilog using dataflow level modeling.
Hint: You can do so succinctly using the ternary operator and the << operator.
(d) Use the code provided below to test the operation of your decoder. Demonstrate your progress
to the TA when complete.
‘ d e f i n e STRLEN 15
module D e c o d e 2 4T e st v ;
t a s k p a s s T e s t ;

i n p u t a ct u al O ut , e x p e ct e d O ut ;
i n p u t [ ‘STRLEN∗ 8 : 0 ] t e s t T y p e ;
i n o u t [ 7 : 0 ] p a s s e d ;
i f ( a c t u a l O u t == e x p e ct e d O ut )
b e gi n
\$ d i s p l a y (”% s p a s s e d ” , t e s t T y p e ) ;
p a s s e d = p a s s e d + 1 ;
end
e l s e

\$ d i s p l a y (”% s f a i l e d : %d s h o ul d be %d ” ,
t e st T y p e , a ct u al O ut , e x p e ct e d O ut ) ;
e n d t a s k
ECEN 651 5
6 Laboratory Exercise #2
t a s k a l l P a s s e d ;
i n p u t [ 7 : 0 ] p a s s e d ;
i n p u t [ 7 : 0 ] n umTe st s ;

i f ( p a s s e d == n umTe st s )
\$ d i s p l a y ( ” All t e s t s p a s s e d ” ) ;
e l s e
\$ d i s p l a y ( ” Some t e s t s f a i l e d ” ) ;
e n d t a s k
/ / I n p u t s
r e g [ 1 : 0 ] i n ;
r e g [ 7 : 0 ] p a s s e d ;
/ / O ut p ut s
wi r e [ 3 : 0 ] o ut ;

/ / I n s t a n t i a t e t h e U nit Under T e st (UUT)
Decode24 u ut (
. i n ( i n ) ,
. o ut ( o ut )
) ;
i n i t i a l b e gi n
/ / I n i t i a l i z e I n p u t s
i n = 0 ;
p a s s e d = 0 ;

/ / Add s t i m u l u s h e r e
# 9 0; i n = 0 ; # 1 0;
p a s s T e s t ( o ut , 1 , ” I n p u t 0 ” , p a s s e d ) ;
# 9 0; i n = 1 ; # 1 0;
p a s s T e s t ( o ut , 2 , ” I n p u t 1 ” , p a s s e d ) ;
# 9 0; i n = 2 ; # 1 0;
p a s s T e s t ( o ut , 4 , ” I n p u t 2 ” , p a s s e d ) ;
# 9 0; i n = 3 ; # 1 0;

p a s s T e s t ( o ut , 8 , ” I n p u t 3 ” , p a s s e d ) ;
a l l P a s s e d ( p a s s e d , 4 ) ;
6 ECEN 651
Laboratory Exercise #2 7
end
endmodule

1 Deliverables
1. Submit a lab report that captures your efforts in lab.
2. Include all Verilog source files with appropriate comments.