Description
Problem 1 [8 points]
Create the schematic and state machine diagram for the direct-mapped caches you will initially be using in
Phase 2.3. As explained above, your memory system schematic should show how the direct-mapped cache,
cache controller, and four-bank memory modules are connected (NOTE: these are the modules you will
eventually use inside mem_system.v in Phase 2.3). And the state machine diagram should show the various
states necessary to correctly operate your cache and the transitions between those states.
Problem 2 [8 points]
Next, we will make our caches two-way set associative. Create the schematic and state machine diagram
for a two-way set associative cache. If you do not need any changes to your state machine diagram from
Problem 1, please submit the same state machine diagram for both problems.
