Description
In this assignment, you are required to extend the MIPS-lite single-cycle implementation (provided
in your lab) by implementing additional instructions. You will use ModelSim simulator to develop
and test your code. The following 10 instructions are to be implemented:
R-format: jr, nor
I-format: addi, andi, bne, bgez, bgtz, bltz
J-format: jal, j
You can find the specifications of the above instructions in the Appendix A of your textbook. You
must design revised single-cycle datapath and control units which make a processor that executes
all 10 instructions as well as the instructions implemented already in the design. You must make
sure that all the instructions working in the current implementation will continue working correctly.
After designing new enhanced processor, you will implement it in Verilog HDL.
You are required to submit a report and commented code. Your report should include the design
details of the revised datapath and control unit with related drawings if necessary. Your
implementation detail should be provided in the source code comment.
Requirements:
You need to justify that the new instructions are being executed correctly by providing
examples. As part of your submission, you are required to give bit sequences representing
new instructions. In your submission, you can include instruction memory module/file with
all instructions your implementation is supporting. Also in your report, you are required to
explain and demonstrate the execution state (content of the registers, PC etc.) after/during
the execution of each instruction.
You are required to submit the source code and a report that includes implementation details.
You need to work individually, no group work is allowed.
No late homework will be accepted.
Submission: You are required to submit all of your files to cloud-lms. Please create a compressed
file including all source files and report; and name it as yourstudentnumber_P3.zip (e.g. If your
student number is 202112345678, the file name must be 202112345678_P3.zip).
