Description
Problem 1 [10 points]
Using Verilog, design an 8 -by -16- bit register file (i.e., 8 registers, each of size 16 bits). See the Verilog
interface below. It has one write port, two read ports, three register select inputs (two for read and one for
write,) a write enable, a reset and a clock input. All register state changes occur on the rising edge of the
clock. Your basic building block must be the D-flipflop given in the provided files. The read ports should
be all combinational logic. Do not use tri-state logic in your design.
Design this register file such that changing the width to 32-bit or 64-bit is straightforward
The read and write data ports are 16 bits each. The select inputs (read and write) are 3 bits each. When the
write enable is asserted (high) the selected register will be written with the data from the write port. The
write occurs on the next rising clock edge; write data cannot flow through to a read port during the same
cycle.
There is no read enable; data from the selected registers will always appear on to the corresponding read
ports.
The reset signal is synchronous and when asserted (active high), resets all the register values to 0.
The err output should be set to 1 if any register (or other sub-module) in the register file has an error. For
now, you may assume that an error only happens in a register if the input or enable is an unknown value,
and in other sub-modules if the input is an unknown value. Otherwise it should be set to 0.
You must use a hierarchical design. Design a 16-bit register first, and then put 8 of them together with
additional logic to build the register file.
Do not make any changes to the provided rf_hier.v file.
Testbench instructions
You must verify your design using the testbench in the supplied tar file and on Github Classroom (of course
you are welcome and encouraged to write additional tests on your own). Run the testbench in your hw5_1
directory using the command: wsrun.pl rf_bench *.v
The testbench for this problem (rf_bench.v) generates a random set of input signals to your module in each
cycle, and compares outputs from your module with outputs that are expected from a perfect register file
implementation.
If there are no errors in your design you will see a “TEST PASSED” message. If the testbench failed with a
“TEST FAILED” message, look for error messages like “ERRORCHECK: Incorrect read data in cycle
” in the testbench output. Above each of these error messages you will see the inputs to
your module, your outputs and the expected outputs for that cycle which can help you debug.
Verify the design using the testbench in the supplied tar file and on Github Classroom.
Problem 2 [10 points]
In Verilog, create a register file that includes internal bypassing so that results written in one cycle can be
read during the same cycle. Do this by writing an outer “wrapper” module that instantiates your existing
(unchanged) register file module; your new module will just add the bypass logic. The list of inputs and
outputs of the outer module should be the same as that of the inner module.
Do not make any changes to the provided rf_hier.v file.
Testbench instructions
You must verify your design using the testbench in the supplied tar file and on Github Classroom (of course
you are welcome and encouraged to write additional tests on your own). Run the testbench in your hw5_2
directory using the command: wsrun.pl rf_bypass_hier_bench *.v
The testbench for this problem (rf_bypass_hier_bench.v) generates a random set of input signals to your
module in each cycle, and compares outputs from your module with outputs that are expected from a perfect
register file bypass implementation.
If there are no errors in your design, you will see a “TEST PASSED” message. If the testbench failed with
a “TEST FAILED WITH xx ERRORS” message, look for error messages like “ERRORCHECK: Read data
incorrect in cycle ” in the testbench output. Above each of these error messages you will
see the inputs to your module, your outputs and the expected outputs for that cycle which can help you
debug.
