Description

CS286 Homework Assignment: Ch2 with Solution

Overview
The purpose of this assignment is to gain familiarity with MIPS assembly language
programming. For this assignment, you will create a MIPS implementation of a bubble
sort algorithm. The program must run in the MIPS simulator and print out the sorted
array.
Simulator
We will use the MARS simulator found here:
https://courses.missouristate.edu/KenVollmar/MARS/download.htm
Other MIPS simulators (notably SPIM and its Javascript implementation JSPIM)
out there. However, our assignemnt requires random number generation which is provided by the MARS simulator, and not the others. MARS is also a bit more intuitive.
You solution must run in the MARS simulator with no errors and it must print out the
sorted numbers.
To invoke the simulator on a linux machine, use the flag to execute a JAR file: java
-jar Mars4_5.jar
Algorithm
You may implement any sort routine you like. Bubble sort is the simplest to implement,
so I suggest that one. A C implementaion of bubble sort is as follows:
Create MIPS assembly code for the following C function. It is an insertion sort
program.
#include <stdio.h>
#include <stdlib.h>
int main(){
int array [5000];
for( int i = 0; i < 5000; i++ )
array[i] = rand()%100;
for(int i = 0; i < 4999; i++)
for( int j =0; j < 4999-i; j++ )
if( array[j+1] < array[j] ){
1
int tmp = array[j];
array[j] = array[j+1];
array[j+1] = tmp;
}
for( int i = 0; i < 5000; i++ )
printf( “%i\n”, array[i]);
}
MIPS Implementation Notes
I am providing a basic file to get you started. You should be able to paste the file into
the MARS simulator and run it. a couple of notes:
syscall
Printing output and generating random numbers are donw via system calls. To execute
a system call, you must put the correct arguments into the $v0, $a0, and $a1 registers.
once those are in the correct place, you simply call syscall. The system call basically
just calls a function, and chooses which function to execute (print, get a random number, etc) via the arguments. The full list of system calls and their arguments are found
here:
https://courses.missouristate.edu/kenvollmar/mars/help/syscallhelp.html
We will use the following system calls:
• code 1 to print integers (put the integer to print in $a0)
• code 4 to print a string (a newline character in our case)
• code 42 to get a random number
The following code shows how to get a random number, then print it
li $a0, 0 # set up random number system call.
# use generator 0
li $a1, 100 # max random number is 100
li $v0, 42 # syscall 42 is random number in a range.
# Result goes in $a0
syscall
li $v0, 1 # set up to print int with syscall number 1
syscall
Allocating Arrays
To allocate an array, we will simply create space on the stack and use that. Remember
that the stack starts at a high address, and grows downwards towards lower addresses.
Therefore, to reserve space for 5 integers on the stack, you simply subtact 20 (4 bytes
per integer times 5 integers) from the stack pointer $sp. you may then use that space
to load and store numbers to. Remember, it is up to you if you want element 0 of your
array to be at the higher address of the space, or the lower address!
2
Labels
To create functions, or points in the code for you to use a branch or jump targets, you
must create a label. A label is simply some text followed by a colon. The following
block demonstrates.
beq $t1, $t0, TARGET
addi $t1, $t1, 5
TARGET:
addi $t0, $t0, 2
To make a function, create a label where the function starts, and then jump and link
to that function:
# the function
FUNC1:
addi $t0, $a1, 10
jr $ra
#call the function
jal FUNC1
Assignment
You must create a MIPS program that runs in the MARS simulator. The program must
do a sort (bubble sort is probably the easiest) and it must sort an array of 30 integers.
The array must be allocated ON THE STACK, as shown above. The program must
print the sorted numbers at the end.
Basic Example Program
The following is a basic example program that allocates an array of 2 integers on the
stack, puts random numbers in it, and prints it out.
.data
NEWLINE: .asciiz “\n”
.text
.globl main #required
main: #required
addi $sp, $sp, -8 # make space for 2 ints, 8 bytes on the stack
li $a0, 0 #set up random number system call. use generator 0
li $a1, 100 # max random number is 100
li $v0, 42 # syscall 42 is random number in a range
syscall # random number is now in $a0
3
sw $a0, 0($sp) # store the number in array location [0]
syscall # random number is now in $a0
sw $a0, 4($sp) # store the number in array location [1]
# NOTE I am making the array atart at a lower address
# and go UP in memory!
#now print out the numbers
li $v0, 1 #set up to print int
lw $a0, 0( $sp ) #get the int to print
syscall
li $v0, 4 #set up to print a string
la $a0, NEWLINE #la is LOAD ADDRESS. newline is declared
#at the start of the program
syscall
li $v0, 1 #set up to print int
lw $a0, 4( $sp ) #get the int to print
syscall
li $v0, 4 #set up to print a string
la $a0, NEWLINE #la is LOAD ADDRESS. newline is declared
#at the start of the program
syscall
li $v0, 10 # last 2 lines are required to make program exit
syscall
4

CS286 MIPS Single Cycle Processor Emulator Project Solution

Description In this project, you will create a simple MIPS simulator. Your simulator will read a binary file containing a MIPS program and execute that program. This will occur in two steps. First, your program will generate the assembly code for the given MIPS program (disassembler). Second, your program will create an instruction-by-instruction simulation of the MIPS program. This simulation will execute instructions sequentially (non-pipelined) and output the contents of all registers and memory (the state of the processor and memory) after each instruction. You will not have to implement exception/interrupt handling You will be given the expected output for each input program. Your output must exactly match the expected output. The program will be graded simply by using the diff program. The diff program simply lists the differences between two files. Your output should have no differences with the expected output. We will suppress white space differences, so if you have a space instead of a tab, that is OK. The command to run diff and suppress white space differences is the following: diff -w Your disassembler can be reused for the next project, so try to write it in a way such that you can separate it from your code to execute the program. In fact, it is easier to write and debug the disassembler first, then write the emulation portion of the project. Implementation You may implement this project in any programming language of your choosing. You MUST include instructions in a README file that indicate how to compile (if necessary) and run your program. You MUST include a makefile to compile the code if it is in a language that requires compilation. Examples are linked on the course web site. Your code will be graded on linux on the home server. The only reason it will not be graded there is if you use such an obscure language that home does not have the correct compilers/interpreters for it. C/C++, and Java program must be able to run on home. You may develop locally, then test on home at the end. This program should require NO system libraries, except I/O, so there should be no trouble. 1 Details Refer to the MIPS instruction set architecture PDF that is posted along with the course notes on the course website. It provides the details for all MIPS instructions. NOTE that we are making the following changes to the instruction set architecture: Instead of a 6 bit opcode, we will use a 5 bit opcode that is preceded by a valid bit. The valid bit will be set to 1 if the instruction is valid and should be executed. If the valid bit is set to 0, then the instruction has no effect (it is effectively a NOP). The opcodes will be the same as those in the MIPS instruction set, just ignore the most significant bit (the first bit). We will not change the functionality of any instruction, simply we use this convention for the opcode. The table below illustrates this change: Bit 31 Bits 30 – 26 Bits 25 – 0 Valid bit Opcode The rest of the instruction A suggestion to make coding the program easier. First, read the entire file and simply print if each instruction is valid or not. This will force you to get the general structure of the disassembler in place and debugged before you begin the more complicated step of disassembly. You will be given an input file containing a sequence of 32 bit instruction words. Assume that the first instruction is at memory address 96. The final instruction in an instruction sequence is ALWAYS a “BREAK” instruction. Following the break instruction is a sequence of 32 bit 2’s compliment signed integers for the program data. These continue until the end of file. Your simulator/disassembler must support the following MIPS instructions. Check the MIPS manual for details on instruction representation and operation for each instruction. J, JR, BEQ, BLTZ ADD, ADDI, SUB SW, LW SLL, SRL MUL, AND, OR, MOVZ NOP Input Your program must accept command line arguments for execution. The following arguments must be supported (Executable named “mipssim”): mipssim –i INPUTFILENAME –o OUTPUTFILENAME Your program will produce 2 output files. One named OUTPUTFILENAME_sim.txt, which contains the simulation output, and one named OUTPUTFILENAME_dis.txt, which contains the disassembled program code for the input MIPS program. 2 Your program will be graded both with the sample input and output provided to you, and with input and output that is not provided to you. It is recommended you construct your own input programs for testing. Output Your program will produce 2 output files. ∙ One named OUTPUTFILENAME_sim.txt, which contains the simulation output ∙ One named OUTPUTFILENAME_dis.txt, which contains the disassembled program code for the input MIPS program. The disassembled output file should contain one line per word in the input file. It should be separated into 4 columns, each separated by tab character. The columns contain the following information: 1. The binary representation of the instruction word. If the word is an instruction (as opposed to memory data after the BREAK instruction), the instruction should be split into seven groups of digits: the valid bit, the opcode bits, four groups of 5 bits, and a final group of 6 bits. 2. The address of the memory location (in decimal) 3. The disassembled instruction opcode 4. If it is an instruction, print the operation, followed by a tab character, then print each argument separated by a comma and a space ( “, “). The simulation file must have the following format: ∙ 20 equal signs and a newline ∙ cycle: [cycle number] [tab] [instruction address] [tab] [instruction string (same as step 4 above)] ∙ [blank lane] ∙ registers: ∙ r00: [tab] [integer value of R00][tab] [integer value of R01][tab] . . . [integer value of R07] ∙ r08: [tab] [integer value of R08][tab] [integer value of R09][tab] . . . [integer value of R15] ∙ r16: [tab] [integer value of R16][tab] [integer value of R17][tab] . . . [integer value of R23] ∙ r24: [tab] [integer value of R24][tab] [integer value of R25][tab] . . . [integer value of R31] ∙ [blank line] 3 ∙ [data address]: [tab] [show 8 data words, with tabs in between] ∙ … [continue until last data word] Hint: Spend some time creating an output function or class or module or whatever fits your language of choice that handles printing out the various data in this format. Spending a little time to do it right in the beginning will save you a lot of time later. Another hint, the register file and memory can simply be implemented as arrays. Go ahead and make them global variables so you don’t have to pass them around to a bunch of functions. This just makes the code a little more simple to write. Instructions and arguments should be in capital letters. All integer values should be in decimal. Immediate values should be preceded by a # sign. Be careful and consider which instructions take signed values and which take unsigned values. Be sure to use the correct format depending on the context. You output will be graded with the diff command. Test your output against the provided sample outputs! Any differences reported by the diff command are assumed to be incorrect output! Sample files will be provided with the following extensions: ∙ .c – C code ∙ .mips – the compiled version of the C code ∙ .bin – the binary version of the .mips file ∙ sample output files ∙ a file named similar to sample_bin.txt which is a text version of the .bin file for your reference. Note that your program must accept the .bin file, not the text version. What to Turn In 1. Your source files, in ZIP or TAR format. 2. A README file in PLAIN TEXT FORMAT that contains the names and email addresses of your group members and instructions for compiling and running your program. The README file should NOT have a file extension (e.g., .txt). 3. A MAKEFILE that will compile your program using the default make target (all:). You may use any programming language you like. If your language of choice is NOT available on the home server, you must demo it to me in my office. The executable must be named “mipssim” once the program is compiled. If your programming language uses an interpreter to execute the program, indicate that in the README file. DO NOT turn in any sample input files or any previously generated output files. 4 Grading A valid attempt at the project that compiles and produces some output is worth 70 points. Each produced disassembly and simulation file is worth 5 points. There are 3 bin files from which 3 disassembly files are produced and 3 simulation files. You will receive 5 points for a produced file if it matches the provided file EXACTLY (with the exception of white space differences). Programs that do not compile or that do not produce any output will get 0 points. If you do not follow the directions in regards to command line arguments or expected behavior, the penalty is at the discretion of the grader. Input and Expected Output The remainder of the document contains PDF versions of the expected output. The input files and text files of the expected output will be available on the course webpage. The final two pages of this document contain programs to convert text files containing binary strings to binary files, and vice versa. Use those programs to develop your own MIPS executables for debugging and testing. Note that your program MUST USE A BINARY FILE AS INPUT. The test1 example contains a text representation of the input file as well as the c version of the program. These are there for informational purposes only. Your program only needs to read the binary file and produce the disassembled file and simulation file. 5 EX_readBinaryFile.cpp Page 1 of 1 #include #include #include #include using namespace std; int main() { char buffer[4]; int i; char * iPtr; iPtr = (char*)(void*) &i; int FD = open(“test2.bin”, O_RDONLY); int amt = 4; while( amt != 0 ) { amt = read(FD, buffer, 4); if( amt == 4) { iPtr[0] = buffer[3]; iPtr[1] = buffer[2]; iPtr[2] = buffer[1]; iPtr[3] = buffer[0]; cout << “i = ” <<hex<< i << endl; } } } 6 EX_readBinaryFile.java Page 1 of 1 import java.io.BufferedInputStream; import java.io.DataInputStream; import java.io.File; import java.io.FileInputStream; import java.io.FileNotFoundException; import java.io.IOException; class EX_readBinaryFile { public static void main(String[] args) throws IOException, FileNotFoundException { File file = new File(“test1.bin”); byte[] fileData = new byte[(int) file.length()]; DataInputStream dis = new DataInputStream(new FileInputStream(file)); dis.readFully(fileData); dis.close(); for( int i = 0; i < fileData.length; i+=4 ) { int x = 0; x = x | ((fileData[i] & 0x000000FF)<<24); x = x | ((fileData[i+1] & 0x000000FF) << 16); x = x | ((fileData[i+2] & 0x000000FF) << 8); x = x | (fileData[i+3] & 0x000000FF); System.out.println(x); System.out.println((x>>26) & 0x0000003F); System.out.println(((x<<6)>>27) & 0x0000001F); System.out.println( Integer.toHexString(x) ); } } } 7 EX_readBinaryFile.py Page 1 of 1 import sys import os import struct # convert ints to signed def imm16BitUnsignedTo32BitSignedConverter( num ): negBitMask = 0x00008000 # if the 16th bit is 1, the 16 bit value is negative if( negBitMask & num ) > 0 : # put 1s in the upper 16 bits num = num | 0xFFFF0000 # now perform a 2’s complement conversion # flip the bits using XOR num = num ^ 0xFFFFFFFF # add 1 num = num + 1 # num is now the positive version of the number # multiply by -1 to get a signed integer with the negative number num = num * -1 return num # how to read binary file and get ints inFile = open( sys.argv[1], ’rb’ ) # get the file length inFileLen = os.stat( sys.argv[1] )[6] inFileWords = inFileLen / 4 instructions = [] address = [] # read the words from the file for i in range( inFileWords ) : instructions.append( struct.unpack(’>I’, inFile.read(4))[0] ) address.append( 96 + (i*4) ) # use I to hold the current instruction I = instructions[ len(instructions)-1 ] # get IMMEDIATE bits IMM = ((I << 16) & 0xFFFFFFFF ) >> 16 IMM = imm16BitUnsignedTo32BitSignedConverter( IMM ) print bin(I) print IMM # get the opcode bits OP = I>>26 print OP # get the RS bits RS = ((I<<6) & 0xFFFFFFFF) >> 27 print RS print ’—-’ inFile.close() 8 b2t.c Page 1 of 1 /******************************************************* This program converts a binary file to a file containing string representations of the 1’s and 0’s in the binfary file. *******************************************************/ // gcc -o b2t b2t.c // Usage ./a.out < inputfile > outputfile #include main( int argc, char** argv) { if ( argc >1 ) fprintf(stderr,”Usage: ./a.out < input_txt > output_bin\n”); char word[32]; unsigned char vals[4]; unsigned char w, div, b; unsigned char tot ; w = 0; while( scanf( “%c”, &tot) != EOF ) { div = 128; for( b=0; b<8; b++ ) { if( tot >= div) { printf( “1” ); tot -= div; } else printf( “0”); div = div/2; } w ++; if ( w == 4 ) { printf(“\n”); w = 0; } } } 9 t2b.c Page 1 of 1 /******************************************************* This program converts a text file containing text strings of 1’s and 0’s to a binary file. for example, the text string: 00000001000000001111111110101010 would result in the following binary sequence (written as hex here) in the output file: 0100FFAA *******************************************************/ // gcc -o t2b t2b.c // Usage ./a.out < inputfile > outputfile #include main( int argc , char **argv ) { if( argc > 1 ) fprintf(stderr,”Usage: ./a.out < input_txt > output_bin\n”); char word[32]; unsigned char vals[4]; int w, mul, b; unsigned char tot ; while( scanf(” %s”, word ) > 0 ) { for( w=0; w<4; w++ ) { mul = 128; tot = 0; for( b=0; b<8; b++ ) { tot += (word[w*8+b]==’1’)*mul; mul = mul/2; } fputc( tot, stdout); } } } 10 test1_bin.txt Page 1 of 1 00100000000000010000000000001010 10100000000000010000000000001010 10101100000000010000000100001000 00001010000000000000000000000000 10001100000000010000000100001000 10000100001000000000000000001100 10000000000000010101000010000000 10001101010000110000000010101100 10001101010001000000000011011000 10001100000001010000000100000100 10000100011000000000000000000010 10000000100001010011000000100010 10001000000000000000000000100110 10000000100001010011000000100000 10101101010001100000000010101100 10100000001000011111111111111111 10101100000000010000000100001000 10001000000000000000000000011100 10000000000000000000000000001101 11111111111111111111111111111111 11111111111111111111111111111110 11111111111111111111111111111101 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 00000000000000000000000000000000 00000000000000000000000000000000 00000000000000000000000000000101 11111111111111111111111111111011 00000000000000000000000000000110 00000000000000000000000000000000 00000000000000000000000000000000 00000000000000000000000000000000 00000000000000000000000000000000 00000000000000000000000000000000 00000000000000000000000000000000 00000000000000000000000000000000 00000000000000000000000000000000 00000000000000000000000000000000 00000000000000000000000000000000 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000000 11 test1_c.txt Page 1 of 1 int A[11] = {-1, -2, -3, 1, 2, 3, 0, 0, 5, -5, 6}; int B[11] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; int C = 1; main() { int i; for (i=10; i>=0; i–) { if (A[i] >= 0) A[i] = B[i] – C; else A[i] = B[i] + C; } } 12 test1_dis.txt Page 1 of 1 0 01000 00000 00001 00000 00000 001010 96 Invalid Instruction 1 01000 00000 00001 00000 00000 001010 100 ADDI R1, R0, #10 1 01011 00000 00001 00000 00100 001000 104 SW R1, 264(R0) 0 00010 10000 00000 00000 00000 000000 108 Invalid Instruction 1 00011 00000 00001 00000 00100 001000 112 LW R1, 264(R0) 1 00001 00001 00000 00000 00000 001100 116 BLTZ R1, #48 1 00000 00000 00001 01010 00010 000000 120 SLL R10, R1, #2 1 00011 01010 00011 00000 00010 101100 124 LW R3, 172(R10) 1 00011 01010 00100 00000 00011 011000 128 LW R4, 216(R10) 1 00011 00000 00101 00000 00100 000100 132 LW R5, 260(R0) 1 00001 00011 00000 00000 00000 000010 136 BLTZ R3, #8 1 00000 00100 00101 00110 00000 100010 140 SUB R6, R4, R5 1 00010 00000 00000 00000 00000 100110 144 J #152 1 00000 00100 00101 00110 00000 100000 148 ADD R6, R4, R5 1 01011 01010 00110 00000 00010 101100 152 SW R6, 172(R10) 1 01000 00001 00001 11111 11111 111111 156 ADDI R1, R1, #-1 1 01011 00000 00001 00000 00100 001000 160 SW R1, 264(R0) 1 00010 00000 00000 00000 00000 011100 164 J #112 1 00000 00000 00000 00000 00000 001101 168 BREAK 11111111111111111111111111111111 172 -1 11111111111111111111111111111110 176 -2 11111111111111111111111111111101 180 -3 00000000000000000000000000000001 184 1 00000000000000000000000000000010 188 2 00000000000000000000000000000011 192 3 00000000000000000000000000000000 196 0 00000000000000000000000000000000 200 0 00000000000000000000000000000101 204 5 11111111111111111111111111111011 208 -5 00000000000000000000000000000110 212 6 00000000000000000000000000000000 216 0 00000000000000000000000000000000 220 0 00000000000000000000000000000000 224 0 00000000000000000000000000000000 228 0 00000000000000000000000000000000 232 0 00000000000000000000000000000000 236 0 00000000000000000000000000000000 240 0 00000000000000000000000000000000 244 0 00000000000000000000000000000000 248 0 00000000000000000000000000000000 252 0 00000000000000000000000000000000 256 0 00000000000000000000000000000001 260 1 00000000000000000000000000000000 264 0 13 test1_mips.txt Page 1 of 1 ; Initially PC is set to 100 ; Data section is right after the code section .text 100 .global _main _main: ADDI R1, R0, #10 ; init i SW R1, VAR_i(R0) ; store i FOR_0: LW R1, VAR_i(R0) BLTZ R1, END_FOR_0 ; i >= 0? SLL R10, R1, #2 ; get correct word boundary LW R3, A(R10) ; read A[i] LW R4, B(R10) ; read B[i] LW R5, C(R0) ; read C BLTZ R3, ELSE_0 ; A[i] >= 0 ? SUB R6, R4, R5 ; B[i] – C J TAIL_0 ELSE_0: ADD R6, R4, R5 ; B[i] + C TAIL_0: SW R6, A(R10) ; rewrite A[i] ADDI R1, R1, #-1 ; i– SW R1, VAR_i(R0) J FOR_0 END_FOR_0: BREAK A: .word -1, -2, -3, 1, 2, 3, 0, 0, 5, -5, 6 B: .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 C: ; let C be 1 .word 1 VAR_i: ; for var i .word 0 14 test1_sim.txt Page 1 of 32 ==================== cycle:1 100 ADDI R1, R0, #10 registers: r00: 0 10 0 0 0 0 0 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 -5 6 0 0 0 0 0 236: 0 0 0 0 0 0 1 0 ==================== cycle:2 104 SW R1, 264(R0) registers: r00: 0 10 0 0 0 0 0 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 -5 6 0 0 0 0 0 236: 0 0 0 0 0 0 1 10 ==================== cycle:3 112 LW R1, 264(R0) registers: r00: 0 10 0 0 0 0 0 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 -5 6 0 0 0 0 0 236: 0 0 0 0 0 0 1 10 ==================== cycle:4 116 BLTZ R1, #48 registers: r00: 0 10 0 0 0 0 0 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 -5 6 0 0 0 0 0 236: 0 0 0 0 0 0 1 10 ==================== cycle:5 120 SLL R10, R1, #2 registers: r00: 0 10 0 0 0 0 0 0 r08: 0 0 40 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 15 test1_sim.txt Page 2 of 32 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 -5 6 0 0 0 0 0 236: 0 0 0 0 0 0 1 10 ==================== cycle:6 124 LW R3, 172(R10) registers: r00: 0 10 0 6 0 0 0 0 r08: 0 0 40 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 -5 6 0 0 0 0 0 236: 0 0 0 0 0 0 1 10 ==================== cycle:7 128 LW R4, 216(R10) registers: r00: 0 10 0 6 0 0 0 0 r08: 0 0 40 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 -5 6 0 0 0 0 0 236: 0 0 0 0 0 0 1 10 ==================== cycle:8 132 LW R5, 260(R0) registers: r00: 0 10 0 6 0 1 0 0 r08: 0 0 40 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 -5 6 0 0 0 0 0 236: 0 0 0 0 0 0 1 10 ==================== cycle:9 136 BLTZ R3, #8 registers: r00: 0 10 0 6 0 1 0 0 r08: 0 0 40 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 -5 6 0 0 0 0 0 236: 0 0 0 0 0 0 1 10 ==================== cycle:10 140 SUB R6, R4, R5 registers: 16 test1_sim.txt Page 3 of 32 r00: 0 10 0 6 0 1 -1 0 r08: 0 0 40 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 -5 6 0 0 0 0 0 236: 0 0 0 0 0 0 1 10 ==================== cycle:11 144 J #152 registers: r00: 0 10 0 6 0 1 -1 0 r08: 0 0 40 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 -5 6 0 0 0 0 0 236: 0 0 0 0 0 0 1 10 ==================== cycle:12 152 SW R6, 172(R10) registers: r00: 0 10 0 6 0 1 -1 0 r08: 0 0 40 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 -5 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 10 ==================== cycle:13 156 ADDI R1, R1, #-1 registers: r00: 0 9 0 6 0 1 -1 0 r08: 0 0 40 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 -5 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 10 ==================== cycle:14 160 SW R1, 264(R0) registers: r00: 0 9 0 6 0 1 -1 0 r08: 0 0 40 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 -5 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 9 17 test1_sim.txt Page 4 of 32 ==================== cycle:15 164 J #112 registers: r00: 0 9 0 6 0 1 -1 0 r08: 0 0 40 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 -5 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 9 ==================== cycle:16 112 LW R1, 264(R0) registers: r00: 0 9 0 6 0 1 -1 0 r08: 0 0 40 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 -5 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 9 ==================== cycle:17 116 BLTZ R1, #48 registers: r00: 0 9 0 6 0 1 -1 0 r08: 0 0 40 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 -5 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 9 ==================== cycle:18 120 SLL R10, R1, #2 registers: r00: 0 9 0 6 0 1 -1 0 r08: 0 0 36 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 -5 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 9 ==================== cycle:19 124 LW R3, 172(R10) registers: r00: 0 9 0 -5 0 1 -1 0 r08: 0 0 36 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 18 test1_sim.txt Page 5 of 32 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 -5 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 9 ==================== cycle:20 128 LW R4, 216(R10) registers: r00: 0 9 0 -5 0 1 -1 0 r08: 0 0 36 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 -5 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 9 ==================== cycle:21 132 LW R5, 260(R0) registers: r00: 0 9 0 -5 0 1 -1 0 r08: 0 0 36 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 -5 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 9 ==================== cycle:22 136 BLTZ R3, #8 registers: r00: 0 9 0 -5 0 1 -1 0 r08: 0 0 36 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 -5 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 9 ==================== cycle:23 148 ADD R6, R4, R5 registers: r00: 0 9 0 -5 0 1 1 0 r08: 0 0 36 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 -5 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 9 ==================== cycle:24 152 SW R6, 172(R10) 19 test1_sim.txt Page 6 of 32 registers: r00: 0 9 0 -5 0 1 1 0 r08: 0 0 36 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 9 ==================== cycle:25 156 ADDI R1, R1, #-1 registers: r00: 0 8 0 -5 0 1 1 0 r08: 0 0 36 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 9 ==================== cycle:26 160 SW R1, 264(R0) registers: r00: 0 8 0 -5 0 1 1 0 r08: 0 0 36 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 8 ==================== cycle:27 164 J #112 registers: r00: 0 8 0 -5 0 1 1 0 r08: 0 0 36 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 8 ==================== cycle:28 112 LW R1, 264(R0) registers: r00: 0 8 0 -5 0 1 1 0 r08: 0 0 36 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 1 -1 0 0 0 0 0 20 test1_sim.txt Page 7 of 32 236: 0 0 0 0 0 0 1 8 ==================== cycle:29 116 BLTZ R1, #48 registers: r00: 0 8 0 -5 0 1 1 0 r08: 0 0 36 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 8 ==================== cycle:30 120 SLL R10, R1, #2 registers: r00: 0 8 0 -5 0 1 1 0 r08: 0 0 32 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 8 ==================== cycle:31 124 LW R3, 172(R10) registers: r00: 0 8 0 5 0 1 1 0 r08: 0 0 32 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 8 ==================== cycle:32 128 LW R4, 216(R10) registers: r00: 0 8 0 5 0 1 1 0 r08: 0 0 32 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 8 ==================== cycle:33 132 LW R5, 260(R0) registers: r00: 0 8 0 5 0 1 1 0 r08: 0 0 32 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 21 test1_sim.txt Page 8 of 32 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 8 ==================== cycle:34 136 BLTZ R3, #8 registers: r00: 0 8 0 5 0 1 1 0 r08: 0 0 32 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 8 ==================== cycle:35 140 SUB R6, R4, R5 registers: r00: 0 8 0 5 0 1 -1 0 r08: 0 0 32 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 8 ==================== cycle:36 144 J #152 registers: r00: 0 8 0 5 0 1 -1 0 r08: 0 0 32 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: 5 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 8 ==================== cycle:37 152 SW R6, 172(R10) registers: r00: 0 8 0 5 0 1 -1 0 r08: 0 0 32 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 8 ==================== cycle:38 156 ADDI R1, R1, #-1 22 test1_sim.txt Page 9 of 32 registers: r00: 0 7 0 5 0 1 -1 0 r08: 0 0 32 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 8 ==================== cycle:39 160 SW R1, 264(R0) registers: r00: 0 7 0 5 0 1 -1 0 r08: 0 0 32 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 7 ==================== cycle:40 164 J #112 registers: r00: 0 7 0 5 0 1 -1 0 r08: 0 0 32 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 7 ==================== cycle:41 112 LW R1, 264(R0) registers: r00: 0 7 0 5 0 1 -1 0 r08: 0 0 32 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 7 ==================== cycle:42 116 BLTZ R1, #48 registers: r00: 0 7 0 5 0 1 -1 0 r08: 0 0 32 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 23 test1_sim.txt Page 10 of 32 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 7 ==================== cycle:43 120 SLL R10, R1, #2 registers: r00: 0 7 0 5 0 1 -1 0 r08: 0 0 28 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 7 ==================== cycle:44 124 LW R3, 172(R10) registers: r00: 0 7 0 0 0 1 -1 0 r08: 0 0 28 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 7 ==================== cycle:45 128 LW R4, 216(R10) registers: r00: 0 7 0 0 0 1 -1 0 r08: 0 0 28 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 7 ==================== cycle:46 132 LW R5, 260(R0) registers: r00: 0 7 0 0 0 1 -1 0 r08: 0 0 28 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 7 ==================== cycle:47 136 BLTZ R3, #8 registers: r00: 0 7 0 0 0 1 -1 0 r08: 0 0 28 0 0 0 0 0 24 test1_sim.txt Page 11 of 32 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 7 ==================== cycle:48 140 SUB R6, R4, R5 registers: r00: 0 7 0 0 0 1 -1 0 r08: 0 0 28 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 7 ==================== cycle:49 144 J #152 registers: r00: 0 7 0 0 0 1 -1 0 r08: 0 0 28 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 0 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 7 ==================== cycle:50 152 SW R6, 172(R10) registers: r00: 0 7 0 0 0 1 -1 0 r08: 0 0 28 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 7 ==================== cycle:51 156 ADDI R1, R1, #-1 registers: r00: 0 6 0 0 0 1 -1 0 r08: 0 0 28 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 7 ==================== 25 test1_sim.txt Page 12 of 32 cycle:52 160 SW R1, 264(R0) registers: r00: 0 6 0 0 0 1 -1 0 r08: 0 0 28 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 6 ==================== cycle:53 164 J #112 registers: r00: 0 6 0 0 0 1 -1 0 r08: 0 0 28 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 6 ==================== cycle:54 112 LW R1, 264(R0) registers: r00: 0 6 0 0 0 1 -1 0 r08: 0 0 28 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 6 ==================== cycle:55 116 BLTZ R1, #48 registers: r00: 0 6 0 0 0 1 -1 0 r08: 0 0 28 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 6 ==================== cycle:56 120 SLL R10, R1, #2 registers: r00: 0 6 0 0 0 1 -1 0 r08: 0 0 24 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 26 test1_sim.txt Page 13 of 32 172: -1 -2 -3 1 2 3 0 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 6 ==================== cycle:57 124 LW R3, 172(R10) registers: r00: 0 6 0 0 0 1 -1 0 r08: 0 0 24 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 6 ==================== cycle:58 128 LW R4, 216(R10) registers: r00: 0 6 0 0 0 1 -1 0 r08: 0 0 24 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 6 ==================== cycle:59 132 LW R5, 260(R0) registers: r00: 0 6 0 0 0 1 -1 0 r08: 0 0 24 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 6 ==================== cycle:60 136 BLTZ R3, #8 registers: r00: 0 6 0 0 0 1 -1 0 r08: 0 0 24 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 6 ==================== cycle:61 140 SUB R6, R4, R5 registers: r00: 0 6 0 0 0 1 -1 0 27 test1_sim.txt Page 14 of 32 r08: 0 0 24 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 6 ==================== cycle:62 144 J #152 registers: r00: 0 6 0 0 0 1 -1 0 r08: 0 0 24 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 0 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 6 ==================== cycle:63 152 SW R6, 172(R10) registers: r00: 0 6 0 0 0 1 -1 0 r08: 0 0 24 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 6 ==================== cycle:64 156 ADDI R1, R1, #-1 registers: r00: 0 5 0 0 0 1 -1 0 r08: 0 0 24 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 6 ==================== cycle:65 160 SW R1, 264(R0) registers: r00: 0 5 0 0 0 1 -1 0 r08: 0 0 24 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 5 28 test1_sim.txt Page 15 of 32 ==================== cycle:66 164 J #112 registers: r00: 0 5 0 0 0 1 -1 0 r08: 0 0 24 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 5 ==================== cycle:67 112 LW R1, 264(R0) registers: r00: 0 5 0 0 0 1 -1 0 r08: 0 0 24 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 5 ==================== cycle:68 116 BLTZ R1, #48 registers: r00: 0 5 0 0 0 1 -1 0 r08: 0 0 24 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 5 ==================== cycle:69 120 SLL R10, R1, #2 registers: r00: 0 5 0 0 0 1 -1 0 r08: 0 0 20 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 5 ==================== cycle:70 124 LW R3, 172(R10) registers: r00: 0 5 0 3 0 1 -1 0 r08: 0 0 20 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 29 test1_sim.txt Page 16 of 32 data: 172: -1 -2 -3 1 2 3 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 5 ==================== cycle:71 128 LW R4, 216(R10) registers: r00: 0 5 0 3 0 1 -1 0 r08: 0 0 20 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 5 ==================== cycle:72 132 LW R5, 260(R0) registers: r00: 0 5 0 3 0 1 -1 0 r08: 0 0 20 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 5 ==================== cycle:73 136 BLTZ R3, #8 registers: r00: 0 5 0 3 0 1 -1 0 r08: 0 0 20 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 5 ==================== cycle:74 140 SUB R6, R4, R5 registers: r00: 0 5 0 3 0 1 -1 0 r08: 0 0 20 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 5 ==================== cycle:75 144 J #152 registers: 30 test1_sim.txt Page 17 of 32 r00: 0 5 0 3 0 1 -1 0 r08: 0 0 20 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 3 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 5 ==================== cycle:76 152 SW R6, 172(R10) registers: r00: 0 5 0 3 0 1 -1 0 r08: 0 0 20 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 5 ==================== cycle:77 156 ADDI R1, R1, #-1 registers: r00: 0 4 0 3 0 1 -1 0 r08: 0 0 20 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 5 ==================== cycle:78 160 SW R1, 264(R0) registers: r00: 0 4 0 3 0 1 -1 0 r08: 0 0 20 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 4 ==================== cycle:79 164 J #112 registers: r00: 0 4 0 3 0 1 -1 0 r08: 0 0 20 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 4 31 test1_sim.txt Page 18 of 32 ==================== cycle:80 112 LW R1, 264(R0) registers: r00: 0 4 0 3 0 1 -1 0 r08: 0 0 20 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 4 ==================== cycle:81 116 BLTZ R1, #48 registers: r00: 0 4 0 3 0 1 -1 0 r08: 0 0 20 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 4 ==================== cycle:82 120 SLL R10, R1, #2 registers: r00: 0 4 0 3 0 1 -1 0 r08: 0 0 16 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 4 ==================== cycle:83 124 LW R3, 172(R10) registers: r00: 0 4 0 2 0 1 -1 0 r08: 0 0 16 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 4 ==================== cycle:84 128 LW R4, 216(R10) registers: r00: 0 4 0 2 0 1 -1 0 r08: 0 0 16 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 32 test1_sim.txt Page 19 of 32 data: 172: -1 -2 -3 1 2 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 4 ==================== cycle:85 132 LW R5, 260(R0) registers: r00: 0 4 0 2 0 1 -1 0 r08: 0 0 16 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 4 ==================== cycle:86 136 BLTZ R3, #8 registers: r00: 0 4 0 2 0 1 -1 0 r08: 0 0 16 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 4 ==================== cycle:87 140 SUB R6, R4, R5 registers: r00: 0 4 0 2 0 1 -1 0 r08: 0 0 16 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 4 ==================== cycle:88 144 J #152 registers: r00: 0 4 0 2 0 1 -1 0 r08: 0 0 16 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 2 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 4 ==================== cycle:89 152 SW R6, 172(R10) 33 test1_sim.txt Page 20 of 32 registers: r00: 0 4 0 2 0 1 -1 0 r08: 0 0 16 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 4 ==================== cycle:90 156 ADDI R1, R1, #-1 registers: r00: 0 3 0 2 0 1 -1 0 r08: 0 0 16 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 4 ==================== cycle:91 160 SW R1, 264(R0) registers: r00: 0 3 0 2 0 1 -1 0 r08: 0 0 16 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 3 ==================== cycle:92 164 J #112 registers: r00: 0 3 0 2 0 1 -1 0 r08: 0 0 16 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 3 ==================== cycle:93 112 LW R1, 264(R0) registers: r00: 0 3 0 2 0 1 -1 0 r08: 0 0 16 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 34 test1_sim.txt Page 21 of 32 236: 0 0 0 0 0 0 1 3 ==================== cycle:94 116 BLTZ R1, #48 registers: r00: 0 3 0 2 0 1 -1 0 r08: 0 0 16 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 3 ==================== cycle:95 120 SLL R10, R1, #2 registers: r00: 0 3 0 2 0 1 -1 0 r08: 0 0 12 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 3 ==================== cycle:96 124 LW R3, 172(R10) registers: r00: 0 3 0 1 0 1 -1 0 r08: 0 0 12 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 3 ==================== cycle:97 128 LW R4, 216(R10) registers: r00: 0 3 0 1 0 1 -1 0 r08: 0 0 12 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 3 ==================== cycle:98 132 LW R5, 260(R0) registers: r00: 0 3 0 1 0 1 -1 0 r08: 0 0 12 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 35 test1_sim.txt Page 22 of 32 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 3 ==================== cycle:99 136 BLTZ R3, #8 registers: r00: 0 3 0 1 0 1 -1 0 r08: 0 0 12 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 3 ==================== cycle:100 140 SUB R6, R4, R5 registers: r00: 0 3 0 1 0 1 -1 0 r08: 0 0 12 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 3 ==================== cycle:101 144 J #152 registers: r00: 0 3 0 1 0 1 -1 0 r08: 0 0 12 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 3 ==================== cycle:102 152 SW R6, 172(R10) registers: r00: 0 3 0 1 0 1 -1 0 r08: 0 0 12 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 3 ==================== cycle:103 156 ADDI R1, R1, #-1 36 test1_sim.txt Page 23 of 32 registers: r00: 0 2 0 1 0 1 -1 0 r08: 0 0 12 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 3 ==================== cycle:104 160 SW R1, 264(R0) registers: r00: 0 2 0 1 0 1 -1 0 r08: 0 0 12 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 2 ==================== cycle:105 164 J #112 registers: r00: 0 2 0 1 0 1 -1 0 r08: 0 0 12 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 2 ==================== cycle:106 112 LW R1, 264(R0) registers: r00: 0 2 0 1 0 1 -1 0 r08: 0 0 12 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 2 ==================== cycle:107 116 BLTZ R1, #48 registers: r00: 0 2 0 1 0 1 -1 0 r08: 0 0 12 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 -1 -1 -1 -1 -1 37 test1_sim.txt Page 24 of 32 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 2 ==================== cycle:108 120 SLL R10, R1, #2 registers: r00: 0 2 0 1 0 1 -1 0 r08: 0 0 8 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 2 ==================== cycle:109 124 LW R3, 172(R10) registers: r00: 0 2 0 -3 0 1 -1 0 r08: 0 0 8 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 2 ==================== cycle:110 128 LW R4, 216(R10) registers: r00: 0 2 0 -3 0 1 -1 0 r08: 0 0 8 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 2 ==================== cycle:111 132 LW R5, 260(R0) registers: r00: 0 2 0 -3 0 1 -1 0 r08: 0 0 8 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 2 ==================== cycle:112 136 BLTZ R3, #8 registers: r00: 0 2 0 -3 0 1 -1 0 r08: 0 0 8 0 0 0 0 0 38 test1_sim.txt Page 25 of 32 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 2 ==================== cycle:113 148 ADD R6, R4, R5 registers: r00: 0 2 0 -3 0 1 1 0 r08: 0 0 8 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 -3 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 2 ==================== cycle:114 152 SW R6, 172(R10) registers: r00: 0 2 0 -3 0 1 1 0 r08: 0 0 8 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 2 ==================== cycle:115 156 ADDI R1, R1, #-1 registers: r00: 0 1 0 -3 0 1 1 0 r08: 0 0 8 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 2 ==================== cycle:116 160 SW R1, 264(R0) registers: r00: 0 1 0 -3 0 1 1 0 r08: 0 0 8 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 1 ==================== 39 test1_sim.txt Page 26 of 32 cycle:117 164 J #112 registers: r00: 0 1 0 -3 0 1 1 0 r08: 0 0 8 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 1 ==================== cycle:118 112 LW R1, 264(R0) registers: r00: 0 1 0 -3 0 1 1 0 r08: 0 0 8 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 1 ==================== cycle:119 116 BLTZ R1, #48 registers: r00: 0 1 0 -3 0 1 1 0 r08: 0 0 8 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 1 ==================== cycle:120 120 SLL R10, R1, #2 registers: r00: 0 1 0 -3 0 1 1 0 r08: 0 0 4 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 1 ==================== cycle:121 124 LW R3, 172(R10) registers: r00: 0 1 0 -2 0 1 1 0 r08: 0 0 4 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 40 test1_sim.txt Page 27 of 32 172: -1 -2 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 1 ==================== cycle:122 128 LW R4, 216(R10) registers: r00: 0 1 0 -2 0 1 1 0 r08: 0 0 4 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 1 ==================== cycle:123 132 LW R5, 260(R0) registers: r00: 0 1 0 -2 0 1 1 0 r08: 0 0 4 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 1 ==================== cycle:124 136 BLTZ R3, #8 registers: r00: 0 1 0 -2 0 1 1 0 r08: 0 0 4 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 1 ==================== cycle:125 148 ADD R6, R4, R5 registers: r00: 0 1 0 -2 0 1 1 0 r08: 0 0 4 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 -2 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 1 ==================== cycle:126 152 SW R6, 172(R10) registers: r00: 0 1 0 -2 0 1 1 0 41 test1_sim.txt Page 28 of 32 r08: 0 0 4 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 1 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 1 ==================== cycle:127 156 ADDI R1, R1, #-1 registers: r00: 0 0 0 -2 0 1 1 0 r08: 0 0 4 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 1 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 1 ==================== cycle:128 160 SW R1, 264(R0) registers: r00: 0 0 0 -2 0 1 1 0 r08: 0 0 4 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 1 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 0 ==================== cycle:129 164 J #112 registers: r00: 0 0 0 -2 0 1 1 0 r08: 0 0 4 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 1 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 0 ==================== cycle:130 112 LW R1, 264(R0) registers: r00: 0 0 0 -2 0 1 1 0 r08: 0 0 4 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 1 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 0 42 test1_sim.txt Page 29 of 32 ==================== cycle:131 116 BLTZ R1, #48 registers: r00: 0 0 0 -2 0 1 1 0 r08: 0 0 4 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 1 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 0 ==================== cycle:132 120 SLL R10, R1, #2 registers: r00: 0 0 0 -2 0 1 1 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 1 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 0 ==================== cycle:133 124 LW R3, 172(R10) registers: r00: 0 0 0 -1 0 1 1 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 1 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 0 ==================== cycle:134 128 LW R4, 216(R10) registers: r00: 0 0 0 -1 0 1 1 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 1 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 0 ==================== cycle:135 132 LW R5, 260(R0) registers: r00: 0 0 0 -1 0 1 1 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 43 test1_sim.txt Page 30 of 32 data: 172: -1 1 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 0 ==================== cycle:136 136 BLTZ R3, #8 registers: r00: 0 0 0 -1 0 1 1 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 1 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 0 ==================== cycle:137 148 ADD R6, R4, R5 registers: r00: 0 0 0 -1 0 1 1 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -1 1 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 0 ==================== cycle:138 152 SW R6, 172(R10) registers: r00: 0 0 0 -1 0 1 1 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 1 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 0 ==================== cycle:139 156 ADDI R1, R1, #-1 registers: r00: 0 -1 0 -1 0 1 1 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 1 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 0 ==================== cycle:140 160 SW R1, 264(R0) registers: 44 test1_sim.txt Page 31 of 32 r00: 0 -1 0 -1 0 1 1 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 1 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 -1 ==================== cycle:141 164 J #112 registers: r00: 0 -1 0 -1 0 1 1 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 1 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 -1 ==================== cycle:142 112 LW R1, 264(R0) registers: r00: 0 -1 0 -1 0 1 1 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 1 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 -1 ==================== cycle:143 116 BLTZ R1, #48 registers: r00: 0 -1 0 -1 0 1 1 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 1 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 -1 ==================== cycle:144 168 BREAK registers: r00: 0 -1 0 -1 0 1 1 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 1 1 -1 -1 -1 -1 -1 204: -1 1 -1 0 0 0 0 0 236: 0 0 0 0 0 0 1 -1 45 test1_sim.txt Page 32 of 32 46 test2_dis.txt Page 1 of 1 1 00010 00000 00000 00000 00000 011010 96 J #104 0 01000 00000 00010 00000 00000 000010 100 Invalid Instruction 1 01000 00000 00001 00000 00001 100100 104 ADDI R1, R0, #100 1 01000 00000 00010 00000 00000 011000 108 ADDI R2, R0, #24 1 00000 00001 00010 00011 00000 100000 112 ADD R3, R1, R2 1 00000 00011 00000 00000 00000 001000 116 JR R3 0 01000 00000 10000 00000 00000 000001 120 Invalid Instruction 1 00000 00001 00010 00100 00000 100010 124 SUB R4, R1, R2 1 00000 00000 00010 00101 00001 000000 128 SLL R5, R2, #1 1 00000 00000 00101 00110 00001 000010 132 SRL R6, R5, #1 1 11100 00010 00110 00111 00000 000010 136 MUL R7, R2, R6 1 01000 00000 01000 00000 00000 000000 140 ADDI R8, R0, #0 1 00000 00100 01000 01001 00000 001010 144 MOVZ R9, R4, R8 1 00000 00000 00000 00000 00000 000000 148 NOP 1 00000 00000 00000 00000 00000 001101 152 BREAK 00000000000000000000000000000001 156 1 00000000000000000000000000000010 160 2 00000000000000000000000000000011 164 3 00000000000000000000000000000100 168 4 47 test2_sim.txt Page 1 of 3 ==================== cycle:1 96 J #104 registers: r00: 0 0 0 0 0 0 0 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 156: 1 2 3 4 ==================== cycle:2 104 ADDI R1, R0, #100 registers: r00: 0 100 0 0 0 0 0 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 156: 1 2 3 4 ==================== cycle:3 108 ADDI R2, R0, #24 registers: r00: 0 100 24 0 0 0 0 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 156: 1 2 3 4 ==================== cycle:4 112 ADD R3, R1, R2 registers: r00: 0 100 24 124 0 0 0 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 156: 1 2 3 4 ==================== cycle:5 116 JR R3 registers: r00: 0 100 24 124 0 0 0 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 156: 1 2 3 4 ==================== cycle:6 124 SUB R4, R1, R2 registers: r00: 0 100 24 124 76 0 0 0 48 test2_sim.txt Page 2 of 3 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 156: 1 2 3 4 ==================== cycle:7 128 SLL R5, R2, #1 registers: r00: 0 100 24 124 76 48 0 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 156: 1 2 3 4 ==================== cycle:8 132 SRL R6, R5, #1 registers: r00: 0 100 24 124 76 48 24 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 156: 1 2 3 4 ==================== cycle:9 136 MUL R7, R2, R6 registers: r00: 0 100 24 124 76 48 24 576 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 156: 1 2 3 4 ==================== cycle:10 140 ADDI R8, R0, #0 registers: r00: 0 100 24 124 76 48 24 576 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 156: 1 2 3 4 ==================== cycle:11 144 MOVZ R9, R4, R8 registers: r00: 0 100 24 124 76 48 24 576 r08: 0 76 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 49 test2_sim.txt Page 3 of 3 156: 1 2 3 4 ==================== cycle:12 148 NOP registers: r00: 0 100 24 124 76 48 24 576 r08: 0 76 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 156: 1 2 3 4 ==================== cycle:13 152 BREAK registers: r00: 0 100 24 124 76 48 24 576 r08: 0 76 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 156: 1 2 3 4 50 test3_dis.txt Page 1 of 1 0 01000 00000 00001 00000 00000 001010 96 Invalid Instruction 1 01000 00000 00001 00000 00000 001010 100 ADDI R1, R0, #10 1 01011 00000 00001 00000 00100 001000 104 SW R1, 264(R0) 0 00010 10000 00000 00000 00000 000000 108 Invalid Instruction 1 00011 00000 00001 00000 00100 001000 112 LW R1, 264(R0) 1 00001 00001 00000 00000 00000 001100 116 BLTZ R1, #48 1 00000 00000 00001 01010 00010 000000 120 SLL R10, R1, #2 1 00011 01010 00011 00000 00010 101100 124 LW R3, 172(R10) 1 00011 01010 00100 00000 00011 011000 128 LW R4, 216(R10) 1 00011 00000 00101 00000 00100 000100 132 LW R5, 260(R0) 1 00001 00011 00000 00000 00000 000010 136 BLTZ R3, #8 1 00000 00100 00101 00110 00000 100010 140 SUB R6, R4, R5 1 00010 00000 00000 00000 00000 100110 144 J #152 1 00000 00100 00101 00110 00000 100000 148 ADD R6, R4, R5 1 01011 01010 00110 00000 00010 101100 152 SW R6, 172(R10) 1 01000 00001 00001 11111 11111 111111 156 ADDI R1, R1, #-1 1 01011 00000 00001 00000 00100 001000 160 SW R1, 264(R0) 1 00010 00000 00000 00000 00000 011100 164 J #112 1 00000 00000 00000 00000 00000 001101 168 BREAK 00000000000000000000000000000001 172 1 00000000000000000000000000000011 176 3 11111111111111111111111111111101 180 -3 11111111111111111111111111111111 184 -1 11111111111111111111111111111110 188 -2 00000000000000000000000000000011 192 3 00000000000000000000000000000000 196 0 00000000000000000000000000000000 200 0 00000000000000000000000000000101 204 5 11111111111111111111111111111011 208 -5 00000000000000000000000000000110 212 6 00000000000000000000000000000000 216 0 00000000000000000000000000000000 220 0 00000000000000000000000000000000 224 0 00000000000000000000000000000000 228 0 00000000000000000000000000000000 232 0 00000000000000000000000000000000 236 0 00000000000000000000000000000000 240 0 00000000000000000000000000000000 244 0 00000000000000000000000000000000 248 0 00000000000000000000000000000000 252 0 00000000000000000000000000000000 256 0 00000000000000000000000000000010 260 2 00000000000000000000000000000000 264 0 51 test3_sim.txt Page 1 of 32 ==================== cycle:1 100 ADDI R1, R0, #10 registers: r00: 0 10 0 0 0 0 0 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 -5 6 0 0 0 0 0 236: 0 0 0 0 0 0 2 0 ==================== cycle:2 104 SW R1, 264(R0) registers: r00: 0 10 0 0 0 0 0 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 -5 6 0 0 0 0 0 236: 0 0 0 0 0 0 2 10 ==================== cycle:3 112 LW R1, 264(R0) registers: r00: 0 10 0 0 0 0 0 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 -5 6 0 0 0 0 0 236: 0 0 0 0 0 0 2 10 ==================== cycle:4 116 BLTZ R1, #48 registers: r00: 0 10 0 0 0 0 0 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 -5 6 0 0 0 0 0 236: 0 0 0 0 0 0 2 10 ==================== cycle:5 120 SLL R10, R1, #2 registers: r00: 0 10 0 0 0 0 0 0 r08: 0 0 40 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 52 test3_sim.txt Page 2 of 32 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 -5 6 0 0 0 0 0 236: 0 0 0 0 0 0 2 10 ==================== cycle:6 124 LW R3, 172(R10) registers: r00: 0 10 0 6 0 0 0 0 r08: 0 0 40 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 -5 6 0 0 0 0 0 236: 0 0 0 0 0 0 2 10 ==================== cycle:7 128 LW R4, 216(R10) registers: r00: 0 10 0 6 0 0 0 0 r08: 0 0 40 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 -5 6 0 0 0 0 0 236: 0 0 0 0 0 0 2 10 ==================== cycle:8 132 LW R5, 260(R0) registers: r00: 0 10 0 6 0 2 0 0 r08: 0 0 40 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 -5 6 0 0 0 0 0 236: 0 0 0 0 0 0 2 10 ==================== cycle:9 136 BLTZ R3, #8 registers: r00: 0 10 0 6 0 2 0 0 r08: 0 0 40 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 -5 6 0 0 0 0 0 236: 0 0 0 0 0 0 2 10 ==================== cycle:10 140 SUB R6, R4, R5 registers: 53 test3_sim.txt Page 3 of 32 r00: 0 10 0 6 0 2 -2 0 r08: 0 0 40 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 -5 6 0 0 0 0 0 236: 0 0 0 0 0 0 2 10 ==================== cycle:11 144 J #152 registers: r00: 0 10 0 6 0 2 -2 0 r08: 0 0 40 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 -5 6 0 0 0 0 0 236: 0 0 0 0 0 0 2 10 ==================== cycle:12 152 SW R6, 172(R10) registers: r00: 0 10 0 6 0 2 -2 0 r08: 0 0 40 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 -5 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 10 ==================== cycle:13 156 ADDI R1, R1, #-1 registers: r00: 0 9 0 6 0 2 -2 0 r08: 0 0 40 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 -5 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 10 ==================== cycle:14 160 SW R1, 264(R0) registers: r00: 0 9 0 6 0 2 -2 0 r08: 0 0 40 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 -5 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 9 54 test3_sim.txt Page 4 of 32 ==================== cycle:15 164 J #112 registers: r00: 0 9 0 6 0 2 -2 0 r08: 0 0 40 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 -5 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 9 ==================== cycle:16 112 LW R1, 264(R0) registers: r00: 0 9 0 6 0 2 -2 0 r08: 0 0 40 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 -5 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 9 ==================== cycle:17 116 BLTZ R1, #48 registers: r00: 0 9 0 6 0 2 -2 0 r08: 0 0 40 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 -5 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 9 ==================== cycle:18 120 SLL R10, R1, #2 registers: r00: 0 9 0 6 0 2 -2 0 r08: 0 0 36 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 -5 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 9 ==================== cycle:19 124 LW R3, 172(R10) registers: r00: 0 9 0 -5 0 2 -2 0 r08: 0 0 36 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 55 test3_sim.txt Page 5 of 32 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 -5 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 9 ==================== cycle:20 128 LW R4, 216(R10) registers: r00: 0 9 0 -5 0 2 -2 0 r08: 0 0 36 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 -5 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 9 ==================== cycle:21 132 LW R5, 260(R0) registers: r00: 0 9 0 -5 0 2 -2 0 r08: 0 0 36 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 -5 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 9 ==================== cycle:22 136 BLTZ R3, #8 registers: r00: 0 9 0 -5 0 2 -2 0 r08: 0 0 36 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 -5 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 9 ==================== cycle:23 148 ADD R6, R4, R5 registers: r00: 0 9 0 -5 0 2 2 0 r08: 0 0 36 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 -5 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 9 ==================== cycle:24 152 SW R6, 172(R10) 56 test3_sim.txt Page 6 of 32 registers: r00: 0 9 0 -5 0 2 2 0 r08: 0 0 36 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 9 ==================== cycle:25 156 ADDI R1, R1, #-1 registers: r00: 0 8 0 -5 0 2 2 0 r08: 0 0 36 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 9 ==================== cycle:26 160 SW R1, 264(R0) registers: r00: 0 8 0 -5 0 2 2 0 r08: 0 0 36 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 8 ==================== cycle:27 164 J #112 registers: r00: 0 8 0 -5 0 2 2 0 r08: 0 0 36 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 8 ==================== cycle:28 112 LW R1, 264(R0) registers: r00: 0 8 0 -5 0 2 2 0 r08: 0 0 36 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 2 -2 0 0 0 0 0 57 test3_sim.txt Page 7 of 32 236: 0 0 0 0 0 0 2 8 ==================== cycle:29 116 BLTZ R1, #48 registers: r00: 0 8 0 -5 0 2 2 0 r08: 0 0 36 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 8 ==================== cycle:30 120 SLL R10, R1, #2 registers: r00: 0 8 0 -5 0 2 2 0 r08: 0 0 32 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 8 ==================== cycle:31 124 LW R3, 172(R10) registers: r00: 0 8 0 5 0 2 2 0 r08: 0 0 32 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 8 ==================== cycle:32 128 LW R4, 216(R10) registers: r00: 0 8 0 5 0 2 2 0 r08: 0 0 32 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 8 ==================== cycle:33 132 LW R5, 260(R0) registers: r00: 0 8 0 5 0 2 2 0 r08: 0 0 32 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 58 test3_sim.txt Page 8 of 32 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 8 ==================== cycle:34 136 BLTZ R3, #8 registers: r00: 0 8 0 5 0 2 2 0 r08: 0 0 32 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 8 ==================== cycle:35 140 SUB R6, R4, R5 registers: r00: 0 8 0 5 0 2 -2 0 r08: 0 0 32 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 8 ==================== cycle:36 144 J #152 registers: r00: 0 8 0 5 0 2 -2 0 r08: 0 0 32 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: 5 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 8 ==================== cycle:37 152 SW R6, 172(R10) registers: r00: 0 8 0 5 0 2 -2 0 r08: 0 0 32 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 8 ==================== cycle:38 156 ADDI R1, R1, #-1 59 test3_sim.txt Page 9 of 32 registers: r00: 0 7 0 5 0 2 -2 0 r08: 0 0 32 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 8 ==================== cycle:39 160 SW R1, 264(R0) registers: r00: 0 7 0 5 0 2 -2 0 r08: 0 0 32 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 7 ==================== cycle:40 164 J #112 registers: r00: 0 7 0 5 0 2 -2 0 r08: 0 0 32 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 7 ==================== cycle:41 112 LW R1, 264(R0) registers: r00: 0 7 0 5 0 2 -2 0 r08: 0 0 32 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 7 ==================== cycle:42 116 BLTZ R1, #48 registers: r00: 0 7 0 5 0 2 -2 0 r08: 0 0 32 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 60 test3_sim.txt Page 10 of 32 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 7 ==================== cycle:43 120 SLL R10, R1, #2 registers: r00: 0 7 0 5 0 2 -2 0 r08: 0 0 28 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 7 ==================== cycle:44 124 LW R3, 172(R10) registers: r00: 0 7 0 0 0 2 -2 0 r08: 0 0 28 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 7 ==================== cycle:45 128 LW R4, 216(R10) registers: r00: 0 7 0 0 0 2 -2 0 r08: 0 0 28 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 7 ==================== cycle:46 132 LW R5, 260(R0) registers: r00: 0 7 0 0 0 2 -2 0 r08: 0 0 28 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 7 ==================== cycle:47 136 BLTZ R3, #8 registers: r00: 0 7 0 0 0 2 -2 0 r08: 0 0 28 0 0 0 0 0 61 test3_sim.txt Page 11 of 32 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 7 ==================== cycle:48 140 SUB R6, R4, R5 registers: r00: 0 7 0 0 0 2 -2 0 r08: 0 0 28 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 7 ==================== cycle:49 144 J #152 registers: r00: 0 7 0 0 0 2 -2 0 r08: 0 0 28 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 0 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 7 ==================== cycle:50 152 SW R6, 172(R10) registers: r00: 0 7 0 0 0 2 -2 0 r08: 0 0 28 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 7 ==================== cycle:51 156 ADDI R1, R1, #-1 registers: r00: 0 6 0 0 0 2 -2 0 r08: 0 0 28 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 7 ==================== 62 test3_sim.txt Page 12 of 32 cycle:52 160 SW R1, 264(R0) registers: r00: 0 6 0 0 0 2 -2 0 r08: 0 0 28 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 6 ==================== cycle:53 164 J #112 registers: r00: 0 6 0 0 0 2 -2 0 r08: 0 0 28 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 6 ==================== cycle:54 112 LW R1, 264(R0) registers: r00: 0 6 0 0 0 2 -2 0 r08: 0 0 28 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 6 ==================== cycle:55 116 BLTZ R1, #48 registers: r00: 0 6 0 0 0 2 -2 0 r08: 0 0 28 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 6 ==================== cycle:56 120 SLL R10, R1, #2 registers: r00: 0 6 0 0 0 2 -2 0 r08: 0 0 24 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 63 test3_sim.txt Page 13 of 32 172: 1 3 -3 -1 -2 3 0 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 6 ==================== cycle:57 124 LW R3, 172(R10) registers: r00: 0 6 0 0 0 2 -2 0 r08: 0 0 24 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 6 ==================== cycle:58 128 LW R4, 216(R10) registers: r00: 0 6 0 0 0 2 -2 0 r08: 0 0 24 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 6 ==================== cycle:59 132 LW R5, 260(R0) registers: r00: 0 6 0 0 0 2 -2 0 r08: 0 0 24 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 6 ==================== cycle:60 136 BLTZ R3, #8 registers: r00: 0 6 0 0 0 2 -2 0 r08: 0 0 24 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 6 ==================== cycle:61 140 SUB R6, R4, R5 registers: r00: 0 6 0 0 0 2 -2 0 64 test3_sim.txt Page 14 of 32 r08: 0 0 24 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 6 ==================== cycle:62 144 J #152 registers: r00: 0 6 0 0 0 2 -2 0 r08: 0 0 24 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 0 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 6 ==================== cycle:63 152 SW R6, 172(R10) registers: r00: 0 6 0 0 0 2 -2 0 r08: 0 0 24 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 6 ==================== cycle:64 156 ADDI R1, R1, #-1 registers: r00: 0 5 0 0 0 2 -2 0 r08: 0 0 24 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 6 ==================== cycle:65 160 SW R1, 264(R0) registers: r00: 0 5 0 0 0 2 -2 0 r08: 0 0 24 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 5 65 test3_sim.txt Page 15 of 32 ==================== cycle:66 164 J #112 registers: r00: 0 5 0 0 0 2 -2 0 r08: 0 0 24 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 5 ==================== cycle:67 112 LW R1, 264(R0) registers: r00: 0 5 0 0 0 2 -2 0 r08: 0 0 24 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 5 ==================== cycle:68 116 BLTZ R1, #48 registers: r00: 0 5 0 0 0 2 -2 0 r08: 0 0 24 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 5 ==================== cycle:69 120 SLL R10, R1, #2 registers: r00: 0 5 0 0 0 2 -2 0 r08: 0 0 20 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 5 ==================== cycle:70 124 LW R3, 172(R10) registers: r00: 0 5 0 3 0 2 -2 0 r08: 0 0 20 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 66 test3_sim.txt Page 16 of 32 data: 172: 1 3 -3 -1 -2 3 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 5 ==================== cycle:71 128 LW R4, 216(R10) registers: r00: 0 5 0 3 0 2 -2 0 r08: 0 0 20 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 5 ==================== cycle:72 132 LW R5, 260(R0) registers: r00: 0 5 0 3 0 2 -2 0 r08: 0 0 20 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 5 ==================== cycle:73 136 BLTZ R3, #8 registers: r00: 0 5 0 3 0 2 -2 0 r08: 0 0 20 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 5 ==================== cycle:74 140 SUB R6, R4, R5 registers: r00: 0 5 0 3 0 2 -2 0 r08: 0 0 20 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 5 ==================== cycle:75 144 J #152 registers: 67 test3_sim.txt Page 17 of 32 r00: 0 5 0 3 0 2 -2 0 r08: 0 0 20 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 3 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 5 ==================== cycle:76 152 SW R6, 172(R10) registers: r00: 0 5 0 3 0 2 -2 0 r08: 0 0 20 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 5 ==================== cycle:77 156 ADDI R1, R1, #-1 registers: r00: 0 4 0 3 0 2 -2 0 r08: 0 0 20 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 5 ==================== cycle:78 160 SW R1, 264(R0) registers: r00: 0 4 0 3 0 2 -2 0 r08: 0 0 20 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 4 ==================== cycle:79 164 J #112 registers: r00: 0 4 0 3 0 2 -2 0 r08: 0 0 20 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 4 68 test3_sim.txt Page 18 of 32 ==================== cycle:80 112 LW R1, 264(R0) registers: r00: 0 4 0 3 0 2 -2 0 r08: 0 0 20 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 4 ==================== cycle:81 116 BLTZ R1, #48 registers: r00: 0 4 0 3 0 2 -2 0 r08: 0 0 20 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 4 ==================== cycle:82 120 SLL R10, R1, #2 registers: r00: 0 4 0 3 0 2 -2 0 r08: 0 0 16 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 4 ==================== cycle:83 124 LW R3, 172(R10) registers: r00: 0 4 0 -2 0 2 -2 0 r08: 0 0 16 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 4 ==================== cycle:84 128 LW R4, 216(R10) registers: r00: 0 4 0 -2 0 2 -2 0 r08: 0 0 16 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 69 test3_sim.txt Page 19 of 32 data: 172: 1 3 -3 -1 -2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 4 ==================== cycle:85 132 LW R5, 260(R0) registers: r00: 0 4 0 -2 0 2 -2 0 r08: 0 0 16 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 4 ==================== cycle:86 136 BLTZ R3, #8 registers: r00: 0 4 0 -2 0 2 -2 0 r08: 0 0 16 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 4 ==================== cycle:87 148 ADD R6, R4, R5 registers: r00: 0 4 0 -2 0 2 2 0 r08: 0 0 16 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 -2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 4 ==================== cycle:88 152 SW R6, 172(R10) registers: r00: 0 4 0 -2 0 2 2 0 r08: 0 0 16 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 4 ==================== cycle:89 156 ADDI R1, R1, #-1 70 test3_sim.txt Page 20 of 32 registers: r00: 0 3 0 -2 0 2 2 0 r08: 0 0 16 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 4 ==================== cycle:90 160 SW R1, 264(R0) registers: r00: 0 3 0 -2 0 2 2 0 r08: 0 0 16 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 3 ==================== cycle:91 164 J #112 registers: r00: 0 3 0 -2 0 2 2 0 r08: 0 0 16 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 3 ==================== cycle:92 112 LW R1, 264(R0) registers: r00: 0 3 0 -2 0 2 2 0 r08: 0 0 16 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 3 ==================== cycle:93 116 BLTZ R1, #48 registers: r00: 0 3 0 -2 0 2 2 0 r08: 0 0 16 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 71 test3_sim.txt Page 21 of 32 236: 0 0 0 0 0 0 2 3 ==================== cycle:94 120 SLL R10, R1, #2 registers: r00: 0 3 0 -2 0 2 2 0 r08: 0 0 12 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 3 ==================== cycle:95 124 LW R3, 172(R10) registers: r00: 0 3 0 -1 0 2 2 0 r08: 0 0 12 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 3 ==================== cycle:96 128 LW R4, 216(R10) registers: r00: 0 3 0 -1 0 2 2 0 r08: 0 0 12 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 3 ==================== cycle:97 132 LW R5, 260(R0) registers: r00: 0 3 0 -1 0 2 2 0 r08: 0 0 12 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 3 ==================== cycle:98 136 BLTZ R3, #8 registers: r00: 0 3 0 -1 0 2 2 0 r08: 0 0 12 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 72 test3_sim.txt Page 22 of 32 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 3 ==================== cycle:99 148 ADD R6, R4, R5 registers: r00: 0 3 0 -1 0 2 2 0 r08: 0 0 12 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 -1 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 3 ==================== cycle:100 152 SW R6, 172(R10) registers: r00: 0 3 0 -1 0 2 2 0 r08: 0 0 12 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 3 ==================== cycle:101 156 ADDI R1, R1, #-1 registers: r00: 0 2 0 -1 0 2 2 0 r08: 0 0 12 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 3 ==================== cycle:102 160 SW R1, 264(R0) registers: r00: 0 2 0 -1 0 2 2 0 r08: 0 0 12 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 2 ==================== cycle:103 164 J #112 73 test3_sim.txt Page 23 of 32 registers: r00: 0 2 0 -1 0 2 2 0 r08: 0 0 12 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 2 ==================== cycle:104 112 LW R1, 264(R0) registers: r00: 0 2 0 -1 0 2 2 0 r08: 0 0 12 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 2 ==================== cycle:105 116 BLTZ R1, #48 registers: r00: 0 2 0 -1 0 2 2 0 r08: 0 0 12 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 2 ==================== cycle:106 120 SLL R10, R1, #2 registers: r00: 0 2 0 -1 0 2 2 0 r08: 0 0 8 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 2 ==================== cycle:107 124 LW R3, 172(R10) registers: r00: 0 2 0 -3 0 2 2 0 r08: 0 0 8 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 2 2 -2 -2 -2 74 test3_sim.txt Page 24 of 32 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 2 ==================== cycle:108 128 LW R4, 216(R10) registers: r00: 0 2 0 -3 0 2 2 0 r08: 0 0 8 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 2 ==================== cycle:109 132 LW R5, 260(R0) registers: r00: 0 2 0 -3 0 2 2 0 r08: 0 0 8 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 2 ==================== cycle:110 136 BLTZ R3, #8 registers: r00: 0 2 0 -3 0 2 2 0 r08: 0 0 8 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 2 ==================== cycle:111 148 ADD R6, R4, R5 registers: r00: 0 2 0 -3 0 2 2 0 r08: 0 0 8 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 -3 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 2 ==================== cycle:112 152 SW R6, 172(R10) registers: r00: 0 2 0 -3 0 2 2 0 r08: 0 0 8 0 0 0 0 0 75 test3_sim.txt Page 25 of 32 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 2 ==================== cycle:113 156 ADDI R1, R1, #-1 registers: r00: 0 1 0 -3 0 2 2 0 r08: 0 0 8 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 2 ==================== cycle:114 160 SW R1, 264(R0) registers: r00: 0 1 0 -3 0 2 2 0 r08: 0 0 8 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 1 ==================== cycle:115 164 J #112 registers: r00: 0 1 0 -3 0 2 2 0 r08: 0 0 8 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 1 ==================== cycle:116 112 LW R1, 264(R0) registers: r00: 0 1 0 -3 0 2 2 0 r08: 0 0 8 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 1 ==================== 76 test3_sim.txt Page 26 of 32 cycle:117 116 BLTZ R1, #48 registers: r00: 0 1 0 -3 0 2 2 0 r08: 0 0 8 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 1 ==================== cycle:118 120 SLL R10, R1, #2 registers: r00: 0 1 0 -3 0 2 2 0 r08: 0 0 4 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 1 ==================== cycle:119 124 LW R3, 172(R10) registers: r00: 0 1 0 3 0 2 2 0 r08: 0 0 4 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 1 ==================== cycle:120 128 LW R4, 216(R10) registers: r00: 0 1 0 3 0 2 2 0 r08: 0 0 4 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 1 ==================== cycle:121 132 LW R5, 260(R0) registers: r00: 0 1 0 3 0 2 2 0 r08: 0 0 4 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 77 test3_sim.txt Page 27 of 32 172: 1 3 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 1 ==================== cycle:122 136 BLTZ R3, #8 registers: r00: 0 1 0 3 0 2 2 0 r08: 0 0 4 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 1 ==================== cycle:123 140 SUB R6, R4, R5 registers: r00: 0 1 0 3 0 2 -2 0 r08: 0 0 4 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 1 ==================== cycle:124 144 J #152 registers: r00: 0 1 0 3 0 2 -2 0 r08: 0 0 4 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 3 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 1 ==================== cycle:125 152 SW R6, 172(R10) registers: r00: 0 1 0 3 0 2 -2 0 r08: 0 0 4 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 -2 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 1 ==================== cycle:126 156 ADDI R1, R1, #-1 registers: r00: 0 0 0 3 0 2 -2 0 78 test3_sim.txt Page 28 of 32 r08: 0 0 4 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 -2 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 1 ==================== cycle:127 160 SW R1, 264(R0) registers: r00: 0 0 0 3 0 2 -2 0 r08: 0 0 4 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 -2 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 0 ==================== cycle:128 164 J #112 registers: r00: 0 0 0 3 0 2 -2 0 r08: 0 0 4 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 -2 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 0 ==================== cycle:129 112 LW R1, 264(R0) registers: r00: 0 0 0 3 0 2 -2 0 r08: 0 0 4 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 -2 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 0 ==================== cycle:130 116 BLTZ R1, #48 registers: r00: 0 0 0 3 0 2 -2 0 r08: 0 0 4 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 -2 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 0 79 test3_sim.txt Page 29 of 32 ==================== cycle:131 120 SLL R10, R1, #2 registers: r00: 0 0 0 3 0 2 -2 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 -2 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 0 ==================== cycle:132 124 LW R3, 172(R10) registers: r00: 0 0 0 1 0 2 -2 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 -2 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 0 ==================== cycle:133 128 LW R4, 216(R10) registers: r00: 0 0 0 1 0 2 -2 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 -2 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 0 ==================== cycle:134 132 LW R5, 260(R0) registers: r00: 0 0 0 1 0 2 -2 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 -2 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 0 ==================== cycle:135 136 BLTZ R3, #8 registers: r00: 0 0 0 1 0 2 -2 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 80 test3_sim.txt Page 30 of 32 data: 172: 1 -2 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 0 ==================== cycle:136 140 SUB R6, R4, R5 registers: r00: 0 0 0 1 0 2 -2 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 -2 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 0 ==================== cycle:137 144 J #152 registers: r00: 0 0 0 1 0 2 -2 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: 1 -2 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 0 ==================== cycle:138 152 SW R6, 172(R10) registers: r00: 0 0 0 1 0 2 -2 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -2 -2 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 0 ==================== cycle:139 156 ADDI R1, R1, #-1 registers: r00: 0 -1 0 1 0 2 -2 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -2 -2 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 0 ==================== cycle:140 160 SW R1, 264(R0) registers: 81 test3_sim.txt Page 31 of 32 r00: 0 -1 0 1 0 2 -2 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -2 -2 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 -1 ==================== cycle:141 164 J #112 registers: r00: 0 -1 0 1 0 2 -2 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -2 -2 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 -1 ==================== cycle:142 112 LW R1, 264(R0) registers: r00: 0 -1 0 1 0 2 -2 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -2 -2 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 -1 ==================== cycle:143 116 BLTZ R1, #48 registers: r00: 0 -1 0 1 0 2 -2 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -2 -2 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 -1 ==================== cycle:144 168 BREAK registers: r00: 0 -1 0 1 0 2 -2 0 r08: 0 0 0 0 0 0 0 0 r16: 0 0 0 0 0 0 0 0 r24: 0 0 0 0 0 0 0 0 data: 172: -2 -2 2 2 2 -2 -2 -2 204: -2 2 -2 0 0 0 0 0 236: 0 0 0 0 0 0 2 -1 82 test3_sim.txt Page 32 of 32 83

OpenMP Programming Assignment CS286 with Solution

Overview: Write a multithreaded C++ program using open MP threads. I will provide a text file containing numbers that must be read into a two dimensional array. The first line of the file will have 2 integers, the number of rows in the array followed by the by the number of columns in the array. The rest of the file will contain integers that the array must be initialized to. Your program must also utilize a random number generator. I will provide source code. Notes on Compiling: This program uses the C++ high resolution timer. It was introduced in the C++ 11 standard, so you may need to explicitly tell the compiler to use the C++ 11 standard. I have included the appropriate option in the example runs below. If you do not wish to compete in the fast time competition, you do not need to include the time information in your output. Description: Your program will indicate the cell address (the row and column) of the cell with the highest neighborhood average. If there is a tie, your program must report only a single cell that ties the maximum value. I will post a solution consisting of all cells that tie the maximum value so you can be sure your solution is correct. The neighborhood of a cell is all cells that immediately border the cell, including the cell itself. For each cell, you must compute the average of numbers in the neighborhood. For example, in the following array: unsigned int M[10000][10000]; the neighborhood of cell M[2][8] consists of the following cells: M[1][7] M[1][8] M[1][9] M[2][7] M[2][8] M[2][9] M[3][7] M[3][8] M[3][9] Because the array will be large, you will need to use dynamic memory allocation (keyword new) on the heap. 1 Be careful not to go out of bounds on the array when computing neighborhoods Your program should take a command line argument indicating the number of threads that will be used. The group that has the fastest program when run with the number of threads equal to the number of available cores on a chosen computer will win a prize (of non-monetary value)! So don’t give away your speedy secrets. The openMP wiki has a nice intro to using openMP. http://en.wikipedia. org/wiki/OpenMP Note that you must have a GCC compiler version 4.3 or later to use openMP. The departrment’s home.cs.siue.edu server has a sufficient GCC version. You can download the newest version of GCC for mac and linux. You may have to install cygwin to do this with windows. Microsoft’s compiler has it too. Sample input files are attached Your program will be graded on home.cs.siue.edu, so make sure it compiles and runs correctly there. Your group must make exactly 1 submission, and your group member names should be in a comment in the first line of your file. Also, you MUST submit a MAKEFILE. A sample makefile is provided, you can use this one, or edit it for your needs. Your submission should be zipped and submitted as single file. What to Turn In: You must turn in your source code, a Makefile that will compile your source code on home.cs.siue.edu, and a README file that contains the names of your group members, and any additional information about your implementation that you think I may need to consider while grading. Turn in a single zip or tar.gz file. The README file should be a PLAIN TEXT FILE! The README must contain the group member names. If you do not wish to try for the fastest time, then you do not need to include time information in your output. Do not include any other information in your output other than what is shown in the example runs! For example, if you print out the entire array in your submission, you will receive a grade of 0 becuase we do not want to spend time parsing through a ton of unneccessary output. Example Input and Expected Output: Here are some sample runs of the program so you can see what the output looks like. Your output should look EXACTLY like mine, except that you will only show a single cell address with the largest average. The input file small3.txt contains two cells tying for the largest average The following shows the expected output with the timing output. You output should match these. These runs were made on an previous instance of the home server, the new home server is substantially faster, so you should be able to beat them. Output that does match the format shown below will recieve a grade of 0. 2 vm-02$ cat Makefile all: g++ -fopenmp -ggdb -std=c++11 matAverager.cpp -o matavg vm-02$ make g++ -fopenmp -ggdb -std=c++11 matAverager.cpp -o matavg vm-02$ ./matavg usage: exe [input data file] [num of threads to use] or usage: exe rand [num of threads to use] [num rows] [num cols] [seed value] vm-02$ ./matavg small3.txt 10 largest average: 7.66667 found at cells: (0,1) (0,2) elapsed time: 0.033653 vm-02$ ./matavg rand 10 5 5 0 largest average: 6780.75 found at cells: (4,4) elapsed time: 0.0271368 vm-02$ ./matavg rand 10 100 100 0 largest average: 8296.33 found at cells: (99,2) elapsed time: 0.0396051 vm-02$ ./matavg rand 10 1000 1000 0 largest average: 9042.44 found at cells: (966,225) elapsed time: 0.08917 vm-02$ ./matavg rand 10 1000 2000 0 largest average: 9339.83 found at cells: (999,1504) elapsed time: 0.080462 vm-02$ ./matavg rand 1 1000 2000 0 largest average: 9339.83 found at cells: (999,1504) elapsed time: 0.162964 vm-02$ ./matavg rand 4 1000 2000 3 largest average: 9370.22 found at cells: (874,617) elapsed time: 0.077152 vm-02$ ./matavg rand 1 1000 2000 3 largest average: 9370.22 found at cells: (874,617) elapsed time: 0.155171 vm-02$ ./matavg rand 10 1000 2000 3 largest average: 9370.22 found at cells: (874,617) elapsed time: 0.0878711 vm-02$ ./matavg rand 10 10000 2000 0 largest average: 9240.89 3 found at cells: (8524,739) elapsed time: 0.336246 vm-02$ ./matavg rand 1 10000 2000 0 largest average: 9240.89 found at cells: (8524,739) elapsed time: 2.0535 vm-02$ ./matavg rand 10 10000 20000 0 largest average: 9461.78 found at cells: (618,2726) elapsed time: 2.48621 vm-02$ Additional Files for this Project: 4 matAverager.cpp Page 1 of 4 #include #include #include #include #include #include #include using namespace std; // a class to get more accurate time class stopwatch{ private: std::chrono::high_resolution_clock::time_point t1; std::chrono::high_resolution_clock::time_point t2; bool timing; public: stopwatch( ): timing( false ) { t1 = std::chrono::high_resolution_clock::time_point::min(); t2 = std::chrono::high_resolution_clock::time_point::min(); } void start( ) { if( !timing ) { timing = true; t1 = std::chrono::high_resolution_clock::now(); } } void stop( ) { if( timing ) { t2 = std::chrono::high_resolution_clock::now(); timing = false; } } void reset( ) { t1 = std::chrono::high_resolution_clock::time_point::min(); t2 = std::chrono::high_resolution_clock::time_point::min();; timing = false; } // will return the elapsed time in seconds as a double double getTime( ) { std::chrono::duration elapsed = std::chrono::duration_cast<std::chrono::duration>(t2-t1); return elapsed.count(); } }; // function takes an array pointer, and the number of rows and cols in the array, and // allocates and intializes the two dimensional array to a bunch of random numbers void makeRandArray( unsigned int **& data, unsigned int rows, unsigned int cols, unsigned int seed ) { // allocate the array data = new unsigned int*[ rows ]; for( unsigned int i = 0; i < rows; i++ ) 5 matAverager.cpp Page 2 of 4 { data[i] = new unsigned int[ cols ]; } // seed the number generator // you should change the seed to get different values srand( seed ); // populate the array for( unsigned int i = 0; i < rows; i++ ) for( unsigned int j = 0; j < cols; j++ ) { data[i][j] = rand() % 10000 + 1; // number between 1 and 10000 } } void getDataFromFile( unsigned int **& data, char fileName[], unsigned int &rows, unsigned int &cols ) { ifstream in; in.open( fileName ); if( !in ) { cerr << “error opening file: ” << fileName << endl; exit( -1 ); } in >> rows >> cols; data = new unsigned int*[ rows ]; for( unsigned int i = 0; i < rows; i++ ) { data[i] = new unsigned int[ cols ]; } // now read in the data for( unsigned int i = 0; i < rows; i++ ) for( unsigned int j = 0; j < cols; j++ ) { in >> data[i][j]; } } int main( int argc, char* argv[] ) { if( argc < 3 ) { cerr<<“Usage: ” << argv[0] << ” [input data file] [num of threads to use] ” << endl; cerr<<“or” << endl << “Usage: “<< argv[0] << ” rand [num of threads to use] [num rows] [num cols] [seed value]” << endl; exit( 0 ); } // read in the file unsigned int rows, cols, seed; unsigned int numThreads; unsigned int ** data; 6 matAverager.cpp Page 3 of 4 // convert numThreads to int { stringstream ss1; ss1 << argv[2]; ss1 >> numThreads; } string fName( argv[1] ); if( fName == “rand” ) { { stringstream ss1; ss1 << argv[3]; ss1 >> rows; } { stringstream ss1; ss1 << argv[4]; ss1 >> cols; } { stringstream ss1; ss1 << argv[5]; ss1 >> seed; } makeRandArray( data, rows, cols, seed ); } else { getDataFromFile( data, argv[1], rows, cols ); } /* //UNCOMMENT if you want to print the data array * cerr << “data: ” << endl; * for( unsigned int i = 0; i < rows; i++ ) * { * for( unsigned int j = 0; j < cols; j++ ) * { * cerr << “i,j,data ” << i << “, ” << j << “, “; * cerr << data[i][j] << ” “; * } * cerr << endl; * } * cerr<< endl; */ // tell omp how many threads to use omp_set_num_threads( numThreads ); stopwatch S1; S1.start(); ///////////////////////////////////////////////////////////////////// /////////////////////// YOUR CODE HERE /////////////////////// /////////////// Make it parallel! //////////////////// ///////////////////////////////////////////////////////////////////// S1.stop(); // print out the max value here 7 matAverager.cpp Page 4 of 4 cerr << “elapsed time: ” << S1.getTime( ) << endl; } 8 Makefile Page 1 of 1 all: g++ -std=c++11 -fopenmp -ggdb matAverager.cpp -o matavg 9 small.txt Page 1 of 1 4 4 4 9 7 4 8 9 5 9 4 2 5 5 9 6 8 2 10 small2.txt Page 1 of 1 10 10 42876 80635 79090 55398 88954 60207 42109 78347 24948 83861 84807 83387 75906 77075 81374 78301 6499 46947 75625 41873 83385 40154 24212 89395 39855 91713 45647 21516 33935 87363 13206 28824 98607 52530 47248 2899 27395 6 70589 4602 65547 69509 56011 41134 87304 40822 80754 88828 55322 46952 24351 74639 4755 74920 52453 91664 18970 94612 71803 28076 93594 29326 67589 31367 55106 75102 26878 97867 30321 25078 21074 98872 65557 67195 17754 83799 67330 56550 94735 61454 93786 39378 73680 20705 85303 83209 78279 63671 54949 34690 49007 50233 64178 84813 53042 7961 7972 20015 28102 86594 11 small3.txt Page 1 of 1 4 4 4 9 7 4 8 9 9 8 4 2 2 4 9 6 6 9 12 numberGen.py Page 1 of 1 import sys import random if len( sys.argv ) >= 4: fileName = sys.argv[1] rows = int( sys.argv[2] ) cols = int( sys.argv[3] ) else: print ’usage: exe [output filename] [num of rows] [num of cols]’ exit() file = open( fileName, ’w’ ) random.seed( ) file.write( str( rows ) + ’ ’ ) file.write( str( cols ) + “\n” ) for i in range( 0,rows ): for j in range( 0, cols ): file.write( str( random.randrange(2,100000) ) ) file.write( ’ ’ ) file.write( “\n” ) 13 timeDiff.bash Page 1 of 1 #!/bin/bash START=$(date +%s) # do something # start your script work here $1 $2 $3 $4 $5 $6 # your logic ends here END=$(date +%s) DIFF=$(( $END – $START )) echo “It took $DIFF seconds” 14